A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

Wu, Jen-Ming; Chen, Yen-Huei; Chang, Meng‐Fan; Chou, Po-Wei; Chen, Chien-Yuan; Liao, Haijun; Chen, Ming-Bin; Chu, Yuan-Hua; Wu, Wen-Chin; Yamauchi, Hiroyuki

doi:10.1109/jssc.2011.2109440

Cited by 75 publications

(17 citation statements)

References 26 publications

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“…Zigzag (Z) 8T SRAM Cell (Wu et al 2010) (Suzuki et al 2010) Figure 2.22 shows a decoupled differential Z8T SRAM cell. It reduces the area overhead associated with CP10T cell and also achieves a better WM.…”

Section: Differential Read Decoupled 8t and 10t Sram Cellsmentioning

confidence: 99%

SRAM Design for Wireless Sensor Networks

Sharma

Catthoor

Dehaene

2013

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Section: Differential Read Decoupled 8t and 10t Sram Cellsmentioning

confidence: 99%

SRAM Design for Wireless Sensor Networks

Sharma

Catthoor

Dehaene

2013

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“…Standby leakage reduction is also critical in enhancing energy efficiency. Bitline leakage elimination techniques [19,20], leakage reduction schemes using sleep transistors [21,22] and multi-V th devices [23,24] have been introduced.…”

Section: Introductionmentioning

confidence: 99%

SRAM devices and circuits optimization toward energy efficiency in multi-V CMOS

Wang

Zhou

Kim

2015

Microelectronics Journal

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“…After Bi-polar junction transistor (BJT), Metal oxide semiconductor field effect transistor (MOSFET) turns the whole VLSI into sparkling path with scaling down the equipment. Multi-gate MOSFET (MuGFET) that was proposed by Sekigawa and Hayashi in 1984 [3]. Then the first DELTA (fully Depleted Lean channel TrAnsistor) was proposed by D Hisamoto in 89s [4].…”

Section: Introductionmentioning

confidence: 99%

Enactment of FinFET Based SRAM with Low Power, Noise and Data Retention at 45 nm Technology

Sable

Akashe

2015

Springer Proceedings in Physics

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In these days, FinFET is getting more preference than CMOS, as it is the most promising transistor known for their high short channel effects controllability and flexible threshold voltage (V th ) through double gate. The major challenge in this era is chip designing in Low Power with scaling of Integrated circuits (IC's). The thinner W fin FinFET show less degradation in performance than thicker W fin . In VLSI, the Area, Power and Delay are major key factors to improve circuit functionality, if any one of that can be reduced then the circuit performance can be enhanced. The types of memories offer Data Retention Voltage (V dr ) variables in FinFET due to different threshold voltage compare to CMOS based memories. This paper investigates implementation of SRAM cell using FinFET to focus on reducing any of the key factors of memory i.e. power dissipation, noise voltage and data retention voltage and also various simulations were carried out between conventional and FinFET based 6T, 7T and 8T SRAM cells. In our proposed FinFET based SRAM cell we get 15-20 % less power dissipation, 6-8 % reduction in data retention voltage and noise voltage reduced up to 30-40 % from conventional SRAM cell, this designing has been done using Cadence Virtuoso tool at 45 nm technology.

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A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

Cited by 75 publications

References 26 publications

SRAM Design for Wireless Sensor Networks

SRAM Design for Wireless Sensor Networks

SRAM devices and circuits optimization toward energy efficiency in multi-V CMOS

Enactment of FinFET Based SRAM with Low Power, Noise and Data Retention at 45 nm Technology

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