A Kriging framework for the efficient exploitation of the nanoscale junctioless DG MOSFETs including source/drain extensions and hot carrier effect

Bentrcia, Toufik; Djeffal, F.; Chebaki, Elasaad; Arar, D.

doi:10.1016/j.matpr.2017.07.007

Cited by 4 publications

(3 citation statements)

References 14 publications

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“…It is worthy to mention that our hybrid framework based on the integration of metamodelling techniques and multi objective optimisation algorithms is a generic approach. Consequently, it has been applied successfully to other important parameters namely gain Av, transconductance generation factor TGF, threshold voltage Vth, swing factor S and OFF-current IOFF [35,36]. Our approach can be also applied to digital performance by including phenomena and mechanisms dominant at subthreshold regime of the device during the simulation phase and performing again the hyperparameters adjustment.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

Approach for designing and modelling of nanoscale DG MOSFET devices using Kriging metamodelling technique

Bentrcia

Djeffal

Chebaki

2017

IET Circuits, Devices & Syst

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In this study, the authors focus mainly on the investigation of Kriging interpolation method to elaborate surrogate models of the nanoscale double-gate metal oxide silicon field effect transistors (DG MOSFET) analogue/RF performance under critical operational conditions. The elaboration of such models is made possible through the generation of computer experiments using ATLAS-2D simulator, where the numerical simulations or experimental measurements, account for the accurate behaviour of the device including the ageing phenomena, short channel and quantum confinement effects. The validity of the obtained Kriging models is tested by comparing the predicted responses of the device with their numerical counterpart in terms of some statistical criteria namely the sum of relative errors, the mean percentage of absolute errors and the correlation coefficient. It is also shown that the obtained Kriging interpolation models are precise enough to be used as objective functions in the context of a genetic algorithm optimisation with the aim of improving the device analogue/RF performance in terms of transconductance and cutoff frequency parameters. Therefore, this study may provide more insights regarding the investigation of surrogate modelling tools in the field of deep nanoscale devices especially with the intractable mission of developing physical based models at this scale for nanoelectronic simulators.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

Approach for designing and modelling of nanoscale DG MOSFET devices using Kriging metamodelling technique

Bentrcia

Djeffal

Chebaki

2017

IET Circuits, Devices & Syst

Self Cite

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“…During the whole simulation process the temperature is set at 300K. The calibration of the simulation model has been performed with the published experimental data [21] and is represented in Fig. 2.…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Influence of oxide thickness variation on analog and RF performances of SOI FinFET

Tripathy

Acharya

Rout³

et al. 2022

FACTA U EE

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This paper focuses on the impact of variation in the thickness of the oxide (SiO2) layer on the performance parameters of a FinFET analysed by varying the oxide layer thickness in the range of 0.8nm to 3nm. While varying the oxide layer thickness, the overall width of the FinFET is fixed at a value 30nm, and the FinFET parameters are analysed for structures with different oxide layer thickness. The parameters like drain current, transconductance, transconductance generation factor, parasitic capacitances, output conductance, cut-off frequency, maximum frequency, GBW, energy and power consumption are calculated to study the influence of FinFET oxide (SiO2) layer thickness variation. It is detected from the result and analysis that the drain current, transconductance, transconductance generation factor, gain bandwidth and output conductance improve with decrement in oxide layer thickness whereas, the parasitic capacitances, cut-off frequency and maximum frequency degrade when there is a reduction in oxide (SiO2) layer thickness. The parameters like energy and consumed power of FinFET get better when the oxide (SiO2) layer thickness increases.

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“…During the whole simulation process the temperature is set at 300K. The simulation model used in this case is calibrated with the experimental data which is published in [34] and is represented in Fig. 2.…”

Section: Device Description and Simulation Modelmentioning

confidence: 99%

Influence of Variation in Oxide layer Thickness on Analog and RF performances of SOI FinFET

Tripathy

Pk³

2021

Preprint

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In this paper, the influence of oxide (SiO2) layer thickness on the different figure of merits of a FinFET is analysed by varying the oxide layer thickness which is present between the gate and the Fin. Here, the overall thickness of the FinFET is taken to be 30nm, and the oxide (SiO2) layer thickness is changed from 0.8 nm to 3nm, and the analog, radio frequency parameters are determined for different structures. The performance parameters like drain current (ID), transconductance generation factor (TGF), transconductance (gm), output conductance (gds), parasitic capacitances like Cgs, Cgd, Cgg, cut-off frequency (fT), gain bandwidth product (GBW) and maximum frequency of oscillation (fmax) are calculated to learn the influence of variation in the FinFET oxide (SiO2) layer thickness. It is detected from the result and analysis that the drain current, output conductance, transconductance generation factor, transconductance and gain bandwidth product improve with decrement in oxide layer thickness. But as a tradeoff, the internal capacitances like Cgs, Cgd, Cgg, maximum frequency of oscillation and cut-off frequency degrade when there is a reduction in oxide (SiO2) layer thickness.

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A Kriging framework for the efficient exploitation of the nanoscale junctioless DG MOSFETs including source/drain extensions and hot carrier effect

Cited by 4 publications

References 14 publications

Approach for designing and modelling of nanoscale DG MOSFET devices using Kriging metamodelling technique

Approach for designing and modelling of nanoscale DG MOSFET devices using Kriging metamodelling technique

Influence of oxide thickness variation on analog and RF performances of SOI FinFET

Influence of Variation in Oxide layer Thickness on Analog and RF performances of SOI FinFET

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