A Kick-Back Reduced Comparator for a 4-6-Bit 3-GS/s Flash ADC in a 90nm CMOS Process

Abstract

This paper presents a kick-back reduced comparator based on a sense-amplifier type comparator. The kickback charge and resulting voltage peak is reduced by 6x, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90nm CMOS process. The significantly lower requirements on input driver and resistance ladder have reduced the overall ADC power dissipation by 50%. Input Reference Comparator Fig. 1. Kick-back from the comparator to the inputs

Utilizing Process Variations for Reference Generation in a Flash ADC

“…This causes a common-mode kickback to the input that could affect subsequent samples. By inserting the clocked transistors in between the cross-coupled inverter pair and the input transistors, the precharge of these internal nodes is prevented, and the common-mode kickback is reduced [14].…”

A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs

“…For a 1 GHz clock and 200 mVpp input range, this input noise results in 3.8 effective bits (ENOB) for a 4-bit ADC design, or 5.2 ENOB for a 6-bit ADC design. The performance of [2] is comparable, keeping the technology scaling in mind, however the stated power consumption does not yet include the power consumption of the reference ladder. The kickback of [3], though not mentioned, is lower than in the proposed design.…”

“…It is less effective in terms of kick-back noise reduction compared to [3], but the reduction is significant, and it does not increase the input noise nor the power consumption. This architecture reuses the idea of offsetting the widths of the input NMOS transistors of the comparators to induce an offset voltage and eliminate the reference ladder, and combines it with cascode transistors [2] to isolate the input differential pair from the regenerative part, and reduce the fast voltage swings across the input transistors. These cascodes separate the calibration capacitors from the drain-gate capacitors of the input differential pair, eliminating the large charge injections to the input nodes and improving the comparator sensitivity, effectively reducing the kick-back noise to clock feed through.…”

“…A down-side of this design is that comparator switching generates considerable kick-back noise into the ADC input, which necessitates the use of a low-impedance buffer for driving the ADC, and so the overall power reduction of this system is limited. Other comparators [2], [3] have been proposed with low kick-back noise. However, these approaches show a relatively high power consumption due to the need for a static reference ladder or due to a folded architecture.…”

A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

“…With the increased number of comparators needed for redundancy this common-mode kick-back cause too large transients on the reference and input voltages. By placing the clocked transistors above the input pair, the pre-charge of these nodes is prevented and the common-mode kick-back charge is reduced by 6x, reducing the power dissipation in the reference ladder and input buffer by the same amount [14].…”