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The major advances in heterojunction bipolar transistor (HBT) technology since the mid‐1980s is covered in this article. The cutoff frequency ( f T ) and the maximum oscillation frequency ( f max ) have reached record highs. Indium phosphide (InP) HBTs have shown ( f T ) and ( f max ) in excess of 450 GHz and gate delays of 1.95 ps. Silicon–germanium (SiGe) HBTs have demonstrated 350 GHz ( f T ) and gate delays of 3.6 ps. The improved performance of the devices has resulted in impressive circuit results. Static frequency dividers operating at 152 GHz has been reported in InP HBT technology. SiGe HBT technology has demonstrated dynamic frequency dividers running at 110 GHz. Multiplexer/demultiplexer (MUX/DMUX) circuits operating at 40 Gbps (gigabits per second) were demonstrated with InP HBTs. On the other hand, 50‐Gbps 4–1 MUX/DMUX circuits have been shown with SiGe HBTs.
The major advances in heterojunction bipolar transistor (HBT) technology since the mid‐1980s is covered in this article. The cutoff frequency ( f T ) and the maximum oscillation frequency ( f max ) have reached record highs. Indium phosphide (InP) HBTs have shown ( f T ) and ( f max ) in excess of 450 GHz and gate delays of 1.95 ps. Silicon–germanium (SiGe) HBTs have demonstrated 350 GHz ( f T ) and gate delays of 3.6 ps. The improved performance of the devices has resulted in impressive circuit results. Static frequency dividers operating at 152 GHz has been reported in InP HBT technology. SiGe HBT technology has demonstrated dynamic frequency dividers running at 110 GHz. Multiplexer/demultiplexer (MUX/DMUX) circuits operating at 40 Gbps (gigabits per second) were demonstrated with InP HBTs. On the other hand, 50‐Gbps 4–1 MUX/DMUX circuits have been shown with SiGe HBTs.
PCLs, shunt stubs, and unit lines have been modified to count for the fringing capacitance and discontinuity effects [10]. The filter shown in Figure 6 is fabricated on a substrate with a relative dielectric constant of 3.38, a loss tangent of 0.0025, and a thickness of 0.8 mm. The filter is rigorously modeled by emulator IE3D [12]. All final characteristic impedances of transmission-lines are obtained by using an optimization process [13]. The simulation results of designed filter performance of pass band with 21% (2.48 GHz) and 10% (5.25 GHz) for duroid substrate. The bandwidths of each passband are highly matched with the desirable values for the filter. The insertion losses of the filter are about 0.731 and 1.403 dB at the frequences of 2.532 and 5.32 GHz, respectively.The measurements are performed with a HP8510C network analyzer. The measured and simulated performances shown in Figure 7 are well matched. From the experimental results, the 3 dB bandwidths are about 20 and 10% for the frequency of 2.45 and 5.25 GHz, respectively. The insertion loss is about 0.831 dB for the frequency of 2.38 GHz and 1.873 dB for the frequency of 5.216 GHz. The proposed filter has attractive features, including wide bandwidth, low insertion loss, smaller size, and easy mass production. CONCLUSIONSIn this investigation, a mapping method to find the system function of a dualband filter in the z-domain by discrete-time domain techniques as well as by chain-scattering matrices of various transmission-lines is developed. By cascading a band-pass filter and a band-stop filter, a dualband filter with the desired bandwidth and low insertion loss is realized. We derive the chain scattering parameters of various microstrip lines and apply the transfer function of transmission lines to design the dual band filter. The validity of the proposed method has been confirmed through the design, simulation, and measurement of dual-band bandpass filter at 2.45-5.25 GHz on duroid substrates. Our design results of the dualband filter is not only easy implementation but also unlimited application to the mentioned bands. It is sensible that many other circuits developed in the digital signal process can also be implemented by using our nonuniform transmission-line method for microwave applications.
This paper proposes a low-phase noise CMOS VCO for more than 10 GHz oscillation, which utilizes a PMOS-bias and PMOS-crosscouple topology. PMOS transistors have lower 1/f noise while they have larger gate capacitance. In this work, a transmission-line resonator is employed to enhance the high-frequency operation. The VCO is fabricated by a 180nm Si CMOS process. A phase noise is -112.6dBc/Hz, and frequency tuning range is 11.8 GHz-12. 4GHz. Power consumption is 8.6mW. Figure of Merit is -184.9 dBc/Hz.
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