Dynamic Reconfigurable Si CMOS VCO Using a Transmission-Line Resonator with PMOS-Bias and PMOS-Crosscouple Topology

Abstract

This paper proposes a low-phase noise CMOS VCO for more than 10 GHz oscillation, which utilizes a PMOS-bias and PMOS-crosscouple topology. PMOS transistors have lower 1/f noise while they have larger gate capacitance. In this work, a transmission-line resonator is employed to enhance the high-frequency operation. The VCO is fabricated by a 180nm Si CMOS process. A phase noise is -112.6dBc/Hz, and frequency tuning range is 11.8 GHz-12. 4GHz. Power consumption is 8.6mW. Figure of Merit is -184.9 dBc/Hz.