2012
DOI: 10.1109/ted.2012.2192499
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A Junctionless Nanowire Transistor With a Dual-Material Gate

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Cited by 147 publications
(28 citation statements)
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“…The channel thickness and width are respectively 10 nm and 20 nm, and the gate length is 1 m. A doping concentration of 210 17 is applied uniformly throughout the source, drain, and channel. SiO2 was chosen as a material for both gate oxide and buried oxide layers.…”
Section: Device Structurementioning
confidence: 99%
See 1 more Smart Citation
“…The channel thickness and width are respectively 10 nm and 20 nm, and the gate length is 1 m. A doping concentration of 210 17 is applied uniformly throughout the source, drain, and channel. SiO2 was chosen as a material for both gate oxide and buried oxide layers.…”
Section: Device Structurementioning
confidence: 99%
“…Single metal gate was replaced by DMG, and the work functions for metal 1 and metal 2 were 4.8 eV (gold) and 4.33 eV (titanium), respectively, considering the values from [16]. The length for both metals was 500 nm [17]. The incorporation of TiN material in between the gate and HfO2 layer [11] is also represented in Fig.…”
Section: Device Structurementioning
confidence: 99%
“…In literature, dual-material gate devices have been widely studied and fabricated [7], [16], [18]- [20]. To realize a DMG architecture, techniques such as tilt angle evaporation and lithography, metal inter-diffusion technique and metal wet etching techniques can be used [18], [21], [22]. In the tilt angle evaporation method, one of the gate material is evaporated with a carefully controlled tilt angle, and then the other material is deposited using conventional evaporation [20].…”
Section: Device Structure and Simulation Setupmentioning
confidence: 99%
“…Due to the increasing development of electronic equipment and being the incessant scaling down of device sizes, semiconductor devices are very close to their physical limits, there is an instantaneous need to develop next-generation technologies, in the designation of both device architecture and physics [1][2]. With the technology of getting smaller which confronts Moore's law i.e., the transistor poll on a chip multiplies at the rate of 2X per every 2 years [3], so nano electronic researchers are greatly keen on studying distinctive nanodevices like carbon nanotube/graphene tunnel field-effect transistors (FETs) and sensors [4][5][6][7][8], organic FETs [9][10], single-molecule devices [11][12], single-electron transistors (SETs) [13][14] and junction-less nanowire transistors [15][16].…”
Section: Introductionmentioning
confidence: 99%