Influence of Tunable Work Function on SOI-based DMG Multi-channel Junctionless Thin Film Transistor

Abstract

This paper focuses on the effects occurring due to the inclusion of multi-channel titanium nitride (TiN) material in a dual metal gate (DMG) junctionless (JL) thin film transistor. Two nanosheets have been implemented in a JL tri-gate transistor, which is separated by the gate oxide layer and surrounded by the gate layer. The thickness of TiN material placed in between the gate oxide and gate layer helps in tuning the work function of the gate. The comparison has been done between single channel with single metal gate, double channel with single metal gate, double channel with DMG and double channel with DMG and TiN. Strains have been created in the devices by implementing TiN and DMG. An improvement of 31 % in the output current has been obtained using DMG double channel device when compared with single gate single channel device. The comparison has been carried out in Sentaurus technology computer aided design (TCAD). The drift diffusion model, the mobility model, which includes the effects of doping concentration and electric field, the bandgap narrowing model and the Shockley-Read-Hall recombination model have been used to calculate outputs. The proposed structure acquires higher transconductance values than normal tri-gate devices. It has been verified that when varying the TiN thickness, the potential has been tuned. Due to the tuning of the work function, the performance of the device has been improved.

Performance Analysis of Incorporating a Buried Metal Layer in a Junction-Less Multi-Channel Field Effect Transistor

“…Using the parameters from [12], a junction-less transistor has been created and simulated in Sentaurus TCAD as seen in Fig. 1.…”

Analysis of Junctionless Nanowire Transistor with Heterojunction, Metal Nitride and Dual Metal Gate

“…The second channel was stacked vertically with the same channel thickness and width. Both channels were separated and surrounded by HfO2 due to suggestion of [14,15]. The inter-oxide layer thickness of 40 nm was determined after running different thickness values, which are shown in Fig.…”

“…This enables improved lifetime of the device [12,13]. The superiority of HfO2 dielectric over other oxide layers has been proven in [14,15] by creating dual metal gates in cylindrical nanowires and analyzing with various gate oxides.…”

Repercussions Through Inclusion of Multi Bridge Channels into Gate All Around Nano-Wire Field Effect Transistor

“…The GAA structure was more appropriate for sub-5 nm devices than FinFET structure according to the reports given in ITRS 2015 [2]. Due to the GAA's exceptional gate control over the channel [3][4], the SCE and leakage current were reduced. Single channel was generated for all the transistors, and the conduction of current took place customarily from source to drain.…”