A jitter characterization system using a component-invariant Vernier delay line

Chan, A.H.; Roberts, G.W.

doi:10.1109/tvlsi.2003.820531

Cited by 104 publications

(66 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Among them, the most typical structure for on-chip jitter measurement is based on the time-to-digital converter (TDC). There are different kinds of TDCs often used, including those that are based on the adjustable delay line [1], [2], the tapped delay line (TDL) [3], the vernier delay line (VDL) [4], [5], the component invariant VDL [6], [18], [22], the vernier ring oscillator (VRO) [8], [9], the time-to-voltage converter (TVC) [14], [20].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement

Xia

Cai

2018

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a design-for-test structure of chargepump phase-locked loops for on-chip jitter measurement, in which use a voltage controlled oscillator based time-to-digital converter. The structure has four key features. 1) By employing a new PFD structure to detect the time difference, it is more suitable for detecting a wide range of timing jitter. 2) The proposed DFT circuit does not need an additional jitter-free reference signal for test using the self-refereed circuit.3) By using a new TDC structure for on-chip jitter measurement of CP-PLL, it achieves a small test area overhead.4) The proposed DFT structure only has a minor modification on the digital part of the CP-PLL, thus it has a little adverse influence on the circuit performance. The experiment result demonstrates its possibility of detecting a timing jitter of 0.78ps with a measurement error of 5.78%.

show abstract

Section: Introductionmentioning

confidence: 99%

“…But it is sensitive to process variations which could degrade the measurement accuracy seriously. In [6], [18], [22] the proposed component invariant VDL eliminated the effect of mismatches of various delay elements. Its resolution was limited by the frequency characteristics of D-type flip-flop.…”

Section: Introductionmentioning

confidence: 99%

A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement

Xia

Cai

2018

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…These circuits are being implemented in PLL-based frequency synthesis systems [1,2], for on-chip PLL jitter measurement [3,4], and for time-of-flight measurement units in particle physics and medical imaging, such as Positron-Emission Tomography (PET) imaging [5]. In all these applications the adaptation of the Vernier method allows to achieve sub-gate delay time resolution.…”

Section: Introductionmentioning

confidence: 99%

“…However, the increased complexity makes the circuits more susceptible to process variation. In order to eliminate the problems caused by the large structures of VDL, single-stage VTDC designs have been proposed [4]. In a single-stage VTDC circuit, the linear VDL has been replaced by a single Vernier stage that consists of two triggerable oscillators featuring different oscillation periods, T s and T f (Figure 1).…”

Section: Introductionmentioning

confidence: 99%

“…The measurement range of the single-stage VTDC is also limited by the detection range of the phase detector. Although the use of single-stage VTDC alleviates the component mismatch problems in the conventional VTDC, the single-stage VTDC can be still unable to achieve sub-gate delay time resolution due to the limitations of the adopted phase detector [4]. This paper presents a single-stage VTDC with a dynamic-logic phase detector that has an extended phase detection range and zero deadzone characteristics, allowing for reliable sub-gate delay time resolution.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

Lin

Syrzycki

2011

View full text Add to dashboard Cite

This paper presents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13 μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6 ns with a time resolution of 25 ps.

show abstract

Time‐to‐digital converters—A comprehensive review

Mattada

Guhilot

2021

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary This work presents a comprehensive literature review on different topologies of time‐to‐digital converters (TDCs). A brief history, applications, classification, characterization, and working principle of each TDC are mentioned. A survey of both Field Programmable Gate Array (FPGA) and Application‐Specific Integrated Circuit (ASIC) architectures is covered. The trade‐off with respect to applications, pros, and cons of different architectures and future scope of TDC as an alternative data converter is also explored.

show abstract

A jitter characterization system using a component-invariant Vernier delay line

Cited by 104 publications

References 13 publications

A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement

A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement

Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

Time‐to‐digital converters—A comprehensive review

Contact Info

Product

Resources

About