A Hybrid Sampling Method for In-the-Loop Yield Estimation of Analog ICs in an Optimization Process

Domanski, Robson; Silva, Luiz Antonio da; Aguirre, Paulo César C. de; Girardi, Alessandro

doi:10.1109/tla.2017.7910189

Cited by 4 publications

(4 citation statements)

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“…These techniques have a faster convergence, causing the number of samples needed to be lower than the value used in MC. The most used techniques are Latin Hypercube Sampling (LHS) [9] and Quasi-Monte Carlo (QMC) [62]. According to [6], LHS needs only 20-25% of the total num-ber of samples needed by the MC.…”

Section: Statistical Analysis For Yield Determinationmentioning

confidence: 99%

“…In other works [3,4,5], the design is carried out through an optimization process with the aim of exploring the solution space for the circuit, using single-and multi-objective optimization heuristics. Some methodologies consider the variability of the manufacturing process and the operating environment during the design stage [6,7,8,9]. At layout level, there are tools that generate the transistor layout and optimize placement and routing to reduce area and the effects of parasites [10].…”

Section: Introductionmentioning

confidence: 99%

“…The second is the availability of good process design kits and device models, providing an accurate characterization of transistor behavior in different operation points. Furthermore, a wide range of statistical models must be made available, including worst-case models, statistical corner models, and Monte Carlo mismatch models, making it possible for circuit design sizing and design centering techniques to achieve high yield and robust designs [9]. The third is a good planning for optimizing the time necessary for a full design cycle, from initial specification to a functional prototype.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Comprehensive Review on Automation-based Sizing Techniques for Analog IC Design

Girardi

De-Oliveira

Ghissoni

et al. 2022

JICS

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Analog integrated circuits are present in most electronic systems. They must be designed carefully in order to achieve the required performance specifications. Although almost half of the design effort in a chip is spent in analog modules, there are not yet a consolidated industry of analog design automation tools capable to fully synthesize analog circuits in a fast and generic way. This is due the fact that automatic or semi-automatic design tools have to deal with high design complexity, which includes several specifications and design variables. A lot of research effort have been done in this field in the past years, proposing methods for automating parts of the design flow, from topology selection to devices sizing and layout generation. This paper presents a review of the state-of-the art in analog design automation methods, focusing on techniques and algorithms used to size robust circuits while efficiently exploring the design space.

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Section: Statistical Analysis For Yield Determinationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Comprehensive Review on Automation-based Sizing Techniques for Analog IC Design

Girardi

De-Oliveira

Ghissoni

et al. 2022

JICS

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“…For example, the authors demonstrated in [10] the advantages of using a genetic algorithm (GA) to design and optimize CMOS operational transconductance amplifiers (OTAs) with robustness. In [11], the authors designed and optimized a two-stage Miller CMOS OTA considering the 130 nm bulk CMOS IC technology node by means of an artificial intelligence heuristic approach in which they proposed a hybrid sampling method to perform the robustness analysis, with a reduced sample size and conventional random sampling. Regarding the work described in [12], the authors proposed a mono-objective metaheuristic (whale optimization algorithm) applied to the optimization of values for the aspect ratios of MOSFETs and the biasing currents of an amplifier intended for lowpower low-voltage biomedical applications.…”

Section: Introductionmentioning

confidence: 99%

Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs

Galembeck¹,

Gimenez

Moreto³

2022

Electronics

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The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer’s experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance.

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A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs

Moreto

Thomaz

Gimenez

2019

Microelectronics Journal

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A Hybrid Sampling Method for In-the-Loop Yield Estimation of Analog ICs in an Optimization Process

Cited by 4 publications

References 0 publications

A Comprehensive Review on Automation-based Sizing Techniques for Analog IC Design

A Comprehensive Review on Automation-based Sizing Techniques for Analog IC Design

Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs

A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs

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