A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels

Zhu, Jianfeng; Liu, Leibo; Yin, Shouyi; Xiao, Yang; Wei, Shaojun

doi:10.1109/tvlsi.2014.2349652

Cited by 9 publications

(5 citation statements)

References 13 publications

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“…Ref. [42] proposed three architectural design techniques to optimize the performance of control flows for CGRAs, including parallel condition, configuration branch and compound configuration. The parallel condition technology increases the instructionlevel parallelism of conditional branches by designing hardware interconnection for control signals.…”

Section: Control Flow Parallelizationmentioning

confidence: 99%

The Principle and Progress of Dynamically Reconfigurable Computing Technologies

Wei

2020

Chin. j. electron.

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Section: Control Flow Parallelizationmentioning

confidence: 99%

The Principle and Progress of Dynamically Reconfigurable Computing Technologies

Wei

2020

Chin. j. electron.

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“…A polyhedral model that is based mapping technology can also be adopted for performance optimization. Taking into account parameters such as dynamic reconfiguration, array calculation and cache access, and using a joint optimization method of affine transformation and loop tiling to establish a performance model and a power consumption model, the execution time of a task can be reduced by about 20% [50] .…”

Section: Cooperation Of Temporal and Spatial Mappingmentioning

confidence: 99%

Architecture, challenges and applications of dynamic reconfigurable computing

Liu

Zhu

et al. 2020

J. Semicond.

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As a computing paradigm that combines temporal and spatial computations, dynamic reconfigurable computing provides superiorities of flexibility, energy efficiency and area efficiency, attracting interest from both academia and industry. However, dynamic reconfigurable computing is not yet mature because of several unsolved problems. This work introduces the concept, architecture, and compilation techniques of dynamic reconfigurable computing. It also discusses the existing major challenges and points out its potential applications.

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“…Parallel condition [6] is an advanced predicated execution which parallelizes condition and computation without reconciliation operations. Control dependence is executed fastest but control divergence is still inefficient for unbalanced branches.…”

Section: Condition-based Full Predication State-based Full Predicatiomentioning

confidence: 99%

“…In order to test the advantage of the proposed approach in handling control flow, a group of control-intensive kernels are selected as benchmark is the same with [6]. Some of the kernels are selected on the basis of an application category called Berkeley Dwarfs [9].…”

Section: Setupmentioning

confidence: 99%

“…Previously, many methods were proposed to address the above problem, such as predication execution [1,2], dual-issue-singleexecution (DISE) [3], Triggered Instruction Architecture (TIA) [4,5], parallel condition [6] and so on. However, there is still no single technique which is optimal across all types of control flow, so composite methods are the only choice [3,7].…”

Section: Introductionmentioning

confidence: 99%

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Acceleration of control flows on reconfigurable architecture with a composite method

Wang

Liu

Zhu

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Control-intensive kernels are becoming the bottleneck that limits the performance of Coarse-Grained Reconfigurable Architecture. Some methods, such as predicated execution, speculative execution, and dual-issue-single-execution, have been proposed to alleviate this problem. But they cannot be always efficient for various control flows. This paper proposes a new architecture, which combines the techniques of triggered instruction and parallel condition, in order to solve the problem completely. The architecture utilizes the basic framework of the triggered instruction to avoid over-serialized execution and branch instruction. Meanwhile, it takes the mechanism of the parallel condition to explore the parallelism between predicate and compute instructions without reconciliation operations. The mechanism of executing multiple instructions that have internal control dependence in parallel is discussed as well. The experiment result shows that the proposed architecture can achieve 20.9% to 140.0% higher performance than that of triggered instruction architecture in terms of cycle count.

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A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels

Cited by 9 publications

References 13 publications

The Principle and Progress of Dynamically Reconfigurable Computing Technologies

The Principle and Progress of Dynamically Reconfigurable Computing Technologies

Architecture, challenges and applications of dynamic reconfigurable computing

Acceleration of control flows on reconfigurable architecture with a composite method

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