The Principle and Progress of Dynamically Reconfigurable Computing Technologies

Wei, Shaojun; Lu, Yanan

doi:10.1049/cje.2020.05.002

Cited by 2 publications

(3 citation statements)

References 66 publications

(110 reference statements)

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“…Reconfigurable logic devices include Coarse‐grained reconfigurable architecture (CGRA) [ 20 ] and Field‐programmable gate array (FPGA) [ 21 ] , which are different in the granularity of customizable circuit components. Although CGRA has certain advantages in terms of reconstruction speed and energy efficiency, it has long design cycle because of the incomplete development ecology.…”

Section: Introductionmentioning

confidence: 99%

A Review of FPGA‐Based Custom Computing Architecture for Convolutional Neural Network Inference

Peng

Yao

et al. 2021

Chinese J of Electronics

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Convolutional neural network (CNN) has been widely adopted in many tasks. Its inference process is usually applied on edge devices where the computing resources and power consumption are limited. At present, the performance of general processors cannot meet the requirement for CNN models with high computation complexity and large number of parameters. Field‐programmable gate array (FPGA)‐based custom computing architecture is a promising solution to further enhance the CNN inference performance. The software/hardware co‐design can effectively reduce the computing overhead, and improve the inference performance while ensuring accuracy. In this paper, the mainstream methods of CNN structure design, hardware‐oriented model compression and FPGA‐based custom architecture design are summarized, and the improvement of CNN inference performance is demonstrated through an example. Challenges and possible research directions in the future are concluded to foster research efforts in this domain.

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Section: Introductionmentioning

confidence: 99%

A Review of FPGA‐Based Custom Computing Architecture for Convolutional Neural Network Inference

Peng

Yao

et al. 2021

Chinese J of Electronics

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“…CGRAs are software-driven reconfigurable processors, specifically driven by data flow [53]. Similar to the architecture presented in this thesis, CGRAs use a message passing architecture.…”

Section: Agp Syntaxmentioning

confidence: 99%

“…Furthermore, the time, expertise, and cost of designing a single ASIC chip is extremely high. As such, many companies and researchers have begun turning to FPGAs to meet the ideal performance, cost, and power consumption balance [4,53]. It is often only in embedded systems with highperformance needs and very limited power restrictions that the industry turn to ASICs.…”

Section: Agp Syntaxmentioning

confidence: 99%

A Message Passing Many-Core Architecture for an Asynchronous Graph Programming Model

Cook¹

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Noticeable improvements in processor performance have been achieved by researching programming models, control flow parallelization, general architecture, memory access, and code compilation [53][4]. In this thesis, we seek to improve general processing by applying a many-core message passing (MPMC) architecture with a novel Asynchronous Graph Programming model (AGP).AGP abstracts higher-level languages into a graph of single instructions providing very high levels of parallelism and asynchronicity. The MPMC architecture utilizes a novel method of segmenting a graph among cores in tandem with the many-core model to exploit AGPs parallelism.We evaluate the MPMC architecture implementing a functional simulation that, although incapable of providing empirical measurements, provides an efficient method of evaluation that helps accelerate the development cycle. We found that the MPMC architecture can reach a 97% improvement in execution time from a single-core configuration, with room to improve given more cores and better node allocation strategies.

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The Principle and Progress of Dynamically Reconfigurable Computing Technologies

Cited by 2 publications

References 66 publications

A Review of FPGA‐Based Custom Computing Architecture for Convolutional Neural Network Inference

A Review of FPGA‐Based Custom Computing Architecture for Convolutional Neural Network Inference

A Message Passing Many-Core Architecture for an Asynchronous Graph Programming Model

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