A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems

Abstract

Abstract-Recent advances in process technology augment the systems-on-chip (SoCs) functionality per unit area with the substantial decrease of device features. However, features abatement triggers new reliability issues such as the single-event multi-bit upset (SMU) failure rates augmentation. To mitigate these failure rates, we propose a novel error mitigation mechanism that relies on a hybrid HW-SW technique. In our proposal, we enforce SoC SRAMs by implementing a fault-tolerant memory buffer with minimal capacity to ensure error-free operation. We utilize this buffer to temporarily store a portion of the stored data, named a data chunk, that is used to restore another data chunk in a fully demand-driven way, in case the latter is faulty. We formulate the buffer and data chunk size selection as an optimization problem that targets energy overhead minimization, given that timing and area overheads are restricted with hard constraints decided beforehand by the system designers. We show that our proposed mitigation scheme achieves full error mitigation in a real SoC platform with an average of 10.1% energy overhead with respect to a base-line system operation, while guaranteeing all the designtime constraints.

Design of Energy Efficient and Dependable Health Monitoring Systems under Unreliable Nanometer Technologies

“…This simulator is based on the cycle accurate MPARM simulator [24], which was utilized and further developed to accommodate error injection, detection and mitigation in our previous work [23]. Note that we consider errors rates (N f ) of the order of 10 -9 down to 10 -6 /cycle which are typical rates reported in recent works [22].…”

“…For instance, in our previous work [23] we showed the effectiveness of combining a small hardware-protected buffer with fine-grained checkpoint and rollback mechanisms. In any case the detection mechanisms of reliability enhancement techniques, such as ECC, can be utilized to monitor the error rates and potentially take system level actions at the software level in case of large error rates.…”

“…Hybrid (Hyb) [23]: the targeted data is divided into chunks, where each chunk is placed in a protected buffer, one at a time to be used whenever an error occurs for successful recovery. These techniques have been used in for reliability mitigation with various error injection rates (10 -9 to 10 -6 bit per cycle).…”

Resolving the memory bottleneck for single supply near-threshold computing

“…We have extended MPARM to provide the support needed for OCEAN. We refer the reader to [17][18] for more details. We use in this analysis a 1K-point FFT, but the analysis is applicable to other streaming applications as well.…”

“…this code is sufficient to detect a double-bit and correct a single-bit error. OCEAN [17][18]: This error correction mechanism is categorized as a cross-layer hybrid SW/HW technique where the mitigation happens demand-driven at run-time. This class of techniques is introduced to minimize the Energy-PerformanceArea (EPA) overheads required to mitigate the increased error rates.…”