A hybrid analog and digital VLSI neural network for intracardiac morphology classification

Coggins, Richard; Jabri, Marwan A.; Flower, B.; Pickard, S.

doi:10.1109/4.384167

Cited by 27 publications

(15 citation statements)

References 12 publications

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“…As described in [6], general hardware platforms for implementing ANNs are classified into some classes like digital [7], analog, hybrid [8], FPGA based [9], or optical implementations. Compared with other platforms, FPGA is one of the most suitable platforms to implement ANN as it offers the parallel computation and re-configurability [10].…”

Section: Introductionmentioning

confidence: 99%

A hybrid layer-multiplexing and pipeline architecture for efficient FPGA-based multilayer neural network

Yang

Lin

et al. 2011

NOLTA

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This paper presents a novel architecture for an FPGA-based implementation of multilayer Artificial Neural Network (ANN), which integrates both the layer-multiplexing and pipeline architecture. Given a kind of FPGA to be used, the proposed method aims at enhancing the efficiency of resource usage of the FPGA and improving the forward speed at the module level, so that a larger ANN can be implemented on traditional FPGAs and also a high performance is achieved. Usually FPGA board is not changed for every applications, thus, we need not mind about the usage of it if the application can be implemented within the resource limitation. We developed a new mapping method from ANN schematic to FPGA by using this hybrid architecture, and also developed an algorithm to automatically determine the architecture by optimizing the application specific neural network topology. The experimental results show that the proposed architecture can produce a very compact circuit for multilayer ANN to meet resource limitation of a given FPGA. Furthermore, higher performance is obtained as compared with conventional methods.

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Section: Introductionmentioning

confidence: 99%

A hybrid layer-multiplexing and pipeline architecture for efficient FPGA-based multilayer neural network

Yang

Lin

et al. 2011

NOLTA

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“…We perform the summation over time dynamically using a bucket brigade device [5]. This device is similar to a CCD line, but is more appropriate for this application, in which the system is clocked at a rate of 1 or 2 ms: while the charge-transfer efficiency in a bucket brigade is less than that of a CCD [6], the CCD is adversely affected by dark currents in the quiescent state and cannot operate at slow (auditory) rates.…”

Section: Bucket Brigadementioning

confidence: 99%

A mixed-signal correlator for acoustic transient classification

Edwards

Cauwenberghs

Pineda

Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97

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Correlation computations are widely used in template-based temporal pattern recognition, but are expensive to compute in real time on DSP systems. We have designed and fabricated a low-power chip which uses current-mode analog circuits to compute the correlation between an auditory input signal in the time-frequency domain and a stored binary template. We use a bucket-brigade device (BBD) to accumulate partial column sums over time at rates consistent with the auditory-band input. Experimental results of the correlator demonstrate its correct operation over a wide range of operating frequencies. I . INTRODUCTIONMany time-based classification systems compute the correlation of an incoming discrete-time signal or signals with a predetermined template [ 11. While for speech and other complex long-term signals it is necessary to perform dynamic time warping (DTW) or similar weighting of the incoming signal [ 2 ] , for transients (short-term acoustic events of less than approximately 1/10 of a second), a simple correlation in the time-frequency domain yields accurate classification results [3].A general form of the simple correlation iswhere M is the number of frequency channels of the input, N is the maximum number of time bins in the window, IC is the array of input signals split into frequency bands, p , is the matrix of template pattern values for pattern z , and t is the current time.This formula produces a running correlation c,[t] of the input array with the template z. For large M and N , this algorithm can be expensive to execute on a DSP in terms of speed and power requirements. However, our approach lends itself elegantly to low-power parallel analog computation in the form of MOS transistor circuits operating primarily in the subthreshold mode.In the following discussion, we present our algorithm as a set of incremental modifications to the baseline algorithm of Equation (1). First, we normalize the input, which is essential for the steps which follow. Next, we take time derivatives of the input and templates, In this form, we are able to make the template values binary without significantly increasing classification error rates. Finally, we move the time-differencing to the output, yielding the simplest possible form of the equation. SIMPLIFYING THE CORRELATION EQUATIONWe assume the input x to the system is an acoustic signal, split into M frequency bands. We compute the (rectified) energy envelope for each band, denoted y, and then normalize these system inputs by the functionwhere 8 is a threshold value included to suppress noise during quiet invervals in the input. Pineda et a1. [4] have shown that the normalized input representation is essential to significantly simplify the pattern classifier algorithm, greatly reducing the size and complexity of the hardware implementation but not degrading the classification result.To make the calmputation less expensive, first we use the time difference between samples of the input and compare it to the difference between samples of the template. The effect of thi...

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“…The neuron circuit then converts the currents back into a differential voltage feeding into the next layer of synapses. Since the outputs of the synapse will all have a common mode component, it is important for the neuron to have common mode cancellation [2]. Since one side of the differential current inputs may have a larger share of the common mode current, it is important to distribute this common mode to keep both differential currents within a reasonable operating range.…”

Section: Neuronmentioning

confidence: 99%

“…This is not a concern because the network will be able to learn around these offsets. The synapse [6], [2] is shown in Figure 2. The synapse performs the weighting of the inputs by multiplying the input voltages by a weight stored in a digital word denoted by b0 through .…”

Section: Synapsementioning

confidence: 99%

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VLSI neural network with digital weights and analog multipliers

Koosh

Goodman

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

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A VLSI feedforward neural network is presented that makes use of digital weights and analog multipliers. The network is trained in a chip-in-loop fashion with a host computer implementing the training algorithm. The chip uses a serial digital weight bus implemented by a long shift register to input the weights. The inputs and outputs of the network are provided directly at pins on the chip. The training algorithm used is a parallel weight perturbation technique [1]. Training results are shown for a 2 input, 1 output network trained with an AND function, and for a 2 input, 2 hidden unit, 1 output network trained with an XOR function.

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A hybrid analog and digital VLSI neural network for intracardiac morphology classification

Cited by 27 publications

References 12 publications

A hybrid layer-multiplexing and pipeline architecture for efficient FPGA-based multilayer neural network

A hybrid layer-multiplexing and pipeline architecture for efficient FPGA-based multilayer neural network

A mixed-signal correlator for acoustic transient classification

VLSI neural network with digital weights and analog multipliers

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