A hybrid layer-multiplexing and pipeline architecture for efficient FPGA-based multilayer neural network

Abstract

This paper presents a novel architecture for an FPGA-based implementation of multilayer Artificial Neural Network (ANN), which integrates both the layer-multiplexing and pipeline architecture. Given a kind of FPGA to be used, the proposed method aims at enhancing the efficiency of resource usage of the FPGA and improving the forward speed at the module level, so that a larger ANN can be implemented on traditional FPGAs and also a high performance is achieved. Usually FPGA board is not changed for every applications, thus, we need not mind about the usage of it if the application can be implemented within the resource limitation. We developed a new mapping method from ANN schematic to FPGA by using this hybrid architecture, and also developed an algorithm to automatically determine the architecture by optimizing the application specific neural network topology. The experimental results show that the proposed architecture can produce a very compact circuit for multilayer ANN to meet resource limitation of a given FPGA. Furthermore, higher performance is obtained as compared with conventional methods.

Efficient On-Chip Learning of Multi-Layer Perceptron Based on Neuron Multiplexing Method

“…Recognizing both the advantages and limitations of pipelining and multiplexing, a proposed integrated architecture that combines these two strategies was presented in [34]. This architecture provides flexibility in selecting between processing speed and resource consumption.…”