A hot hole-induced low-level leakage current in thin silicon dioxide films

Matsukawa, N.; Yamada, Shigeru; Amemiya, Kenta; Hazama, H.

doi:10.1109/16.543028

Cited by 30 publications

(12 citation statements)

References 16 publications

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“…They propose a model in which the presence of holes and neutral oxide traps are a necessary condition for the SILC to occur. Matsukawa et al 30 have shown that hot hole induced low-level leakage current is reduced by hot electron injection and UV irradiation. They conclude that the most probable origin of leak sites may be positive trapped holes.…”

Section: Introductionmentioning

confidence: 99%

Stress-induced leakage current reduction by a low field of opposite polarity to the stress field

Meinertzhagen

Petit

Jourdain

et al. 1998

Journal of Applied Physics

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Stress-induced leakage currents in 7 and 12 nm thick gate oxides of metal-oxide-semiconductor capacitors, created by negative or positive high field stress, were investigated in details. It is known that stress-induced leakage currents have several components. One of these components, which is observed for both stress and measurement polarities, increases drastically when the oxide thickness decreases. We have observed that this component magnitude is reduced when a low field of opposite polarity to the stress field is applied to the oxide after stress. This effect does not seem to be due to electron trapping in the oxide bulk, during the low field application. We propose therefore, that this current decrease is due to a defect relaxation phenomena induced by the low field. This proposition is compatible with any defect creation process which involves a stress-field-induced motion of atoms.

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Section: Introductionmentioning

confidence: 99%

Stress-induced leakage current reduction by a low field of opposite polarity to the stress field

Meinertzhagen

Petit

Jourdain

et al. 1998

Journal of Applied Physics

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“…trapped-hole annealing, based on the presumption that SILC is considerably enhanced in the presence of trapped holes. In fact, several authors have claimed that trapped holes play an important role in SILC, either by positive charge-assisted tunneling mechanism, [9][10][11] trapped-hole enhanced TAT mechanism, 12 or trapped-hole induced tunneling sites 13 ; 3. electron trapping at electron traps which do not act as tunneling sites, assuming that these trapped electrons can suppress TAT mechanism and hence, cause the SILC to reduce. Among the three mechanisms, it is obvious that mechanisms 1 and 3 which involve only electron trapping, do not cause any annihilation of defects.…”

Section: Discussionmentioning

confidence: 99%

“…[10][11][12] Nevertheless, these annealing methodologies which basically inject electrons into an oxide, may introduce electron trapping as well. Therefore, their results were insufficient to infer definitely which mechanism is responsible for the bias annealing of SILC.…”

Section: Discussionmentioning

confidence: 99%

Annealing of Fowler-Nordheim Stress-Induced Leakage Currents in Thin Silicon Dioxide Films

Ang

Ling

Cheng

et al. 2000

J. Electrochem. Soc.

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Electrical stress-induced leakage current (SILC) is a major concern for the reliability of metal oxide semiconductor (MOS) devices with thin gate oxide films. It is responsible for the increased charge loss and data retention degradation in electrically erasable programmable read only memory devices. 1 In general, SILC can be classified into two main components. The first component is transient in nature and dominates the SILC in thicker oxides (>10 nm). It is due to the charging/discharging of near-interfacial neutral electron traps (NETs). [2][3][4] The second component conducts completely through an oxide and dominates the SILC in thin oxides (<5 nm ). This component is usually regarded as a dc current and attributed to trap-assisted tunneling (TAT) mediated by stress-generated NETs. 2,5-8 However, several researchers have claimed that trapped holes also contribute significantly to the second component of SILC. 9-13 Therefore, the origin of second component still remains controversial at this moment and is the subject of investigation in this paper.The study on the annealing of SILC not only sheds more insight into the origin of SILC, but may have potential practical applications in suppressing SILC in nonvolatile memory devices. The annealing of SILC under different conditions has been reported. 10-20 One of them, denoted in this paper as bias annealing, subjects a previously stressed oxide to a low gate bias at room temperature. To date, bias annealing of Fowler-Nordheim (FN) SILC is only reported for the case where the applied gate bias has opposite polarity to the stress field and the oxide thickness is larger than 7 nm. 13-15 Moreover, there is still no general agreement on the mechanism of bias annealing. Endoh et al. attributed the positive bias annealing of SILC following negative bias stress to the deactivation of trapped-hole induced tunneling sites by the injected electrons from the substrate. 13 However, Meinertzhagen et al. proposed that bias annealing reduced the amount of NETs due to reverse-field induced structural relaxation of traps, and argued that the bias annealing of SILC was neither due to electron trapping nor trapped-hole annihilation. 14,15 SILC can also be annealed by thermal annealing at elevated temperature. 1,16-20 Riess et al. have observed that thermal annealing of SILC was enhanced in the presence of oxide field and hence inferred that the mechanism of thermal annealing was due to the out-diffusion of electrically charged species. 20 However, their observations were of net combined effects of bias and thermal annealing on SILC.The purpose of this paper is to study the bias and thermal annealings of SILC in thin gate oxides (4.5 nm), and clarify their mechanisms. We report that SILC can be annealed with the applied gate bias having the same polarity as the stress field. This result disagrees with the previous study which reported that a low field of same polarity to the stress field had no influence on the SILC. 14 In addition, we show that bias annealing of SILC was significant...

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“…Matsukawa et al 28 and Zous et al 29 have reported that the presence of positive oxide trapped charges are responsible for the transient SILC. However, the transient SILC was observed by the above authors in much thicker oxides of 9.3-10 nm thickness.…”

Section: Transient Stress-induced Leakage Currentmentioning

confidence: 99%

“…This indicates that the transient SILC observed does not purely arise from the recombination of positive oxide trapped charges. The positive charge trap-assisted tunneling that has been used to explain the transient SILC mechanism in thick oxides 28,29 could be employed here to explain the transient SILC observed in thin oxides. The above results are further discussed as follows.…”

Section: Transient Stress-induced Leakage Currentmentioning

confidence: 99%

Hole injection with limited charge relaxation, lateral nonuniform hole trapping, and transient stress-induced leakage current in impulse-stressed thin (<5 nm) nitrided oxides

Chim

Lim

2002

Journal of Applied Physics

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Articles you may be interested inModeling the trap generation and relaxation effects in thin oxides under unipolar and bipolar high-field impulse stressing using stress-induced leakage current An anomalously high density of positive trapped charges was observed in thin ͑4.3-nm thickness͒ nitrided gate oxides subjected to high-field impulse stressing. Additionally, the transient stress-induced leakage current ͑AC-SILC͒ was found to be larger than the steady-state SILC ͑DC-SILC͒ in these impulse-stressed thin oxides, contrary to observations in dc-stressed thin oxides. The large AC-SILC was found to be related to the high density of positive trapped holes in the oxide. The hot-hole generation occurs via a regenerative feedback mechanism, with minimal charge relaxation due to the short duration of the impulse stress. This gives rise to an extremely high density of oxide trapped holes that were not observed under dc stress conditions. The trapped holes can be easily annealed electrically at room temperature and the annihilation of the positive oxide trapped charges is accompanied by a reduction in the AC-SILC and a higher number of interface states being created. The trapped holes can either be uniformly or nonuniformly distributed, depending on the polarity of the applied stressing impulse in relation to the substrate doping type. A better understanding of thin oxide degradation under impulse stressing can help in the choice of a suitable write/erase pulse amplitude and duration for use in endurance testing of nonvolatile semiconductor memories to ensure long-term reliable operation.

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A hot hole-induced low-level leakage current in thin silicon dioxide films

Cited by 30 publications

References 16 publications

Stress-induced leakage current reduction by a low field of opposite polarity to the stress field

Stress-induced leakage current reduction by a low field of opposite polarity to the stress field

Annealing of Fowler-Nordheim Stress-Induced Leakage Currents in Thin Silicon Dioxide Films

Hole injection with limited charge relaxation, lateral nonuniform hole trapping, and transient stress-induced leakage current in impulse-stressed thin (<5 nm) nitrided oxides

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A hot hole-induced low-level leakage current in thin silicon dioxide films

Cited by 30 publications

References 16 publications

Stress-induced leakage current reduction by a low field of opposite polarity to the stress field

Stress-induced leakage current reduction by a low field of opposite polarity to the stress field

Annealing of Fowler-Nordheim Stress-Induced Leakage Currents in Thin Silicon Dioxide Films

Hole injection with limited charge relaxation, lateral nonuniform hole trapping, and transient stress-induced leakage current in impulse-stressed thin (&lt;5 nm) nitrided oxides

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Hole injection with limited charge relaxation, lateral nonuniform hole trapping, and transient stress-induced leakage current in impulse-stressed thin (<5 nm) nitrided oxides