A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

Marella, Sravan K.; Kumar, Sanjay; Sapatnekar, Sachin S.

doi:10.1145/2429384.2429450

Cited by 15 publications

(10 citation statements)

References 12 publications

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“…3.1.1.3 Thermal stress: The mismatch between the Coefficient of Thermal Expansion (CTE) of a TSV fill material and the silicon induces a residual thermal stress in the region surrounding the TSV [29], [30]. The thermal stresses can drive interfacial delamination between the TSV and the Si matrix, damaging for the on-chip wiring structures [31], [32].…”

Section: Tsv Issuesmentioning

confidence: 99%

Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip

Eghbal

Bagherzadeh

Khayambashi

2015

IEEE Trans. Comput.

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Reliability is one of the most challenging problems in the context of Three-Dimensional Network-on-Chip (3D NoC) systems. Reliability analysis is prominent for early stages of the manufacturing process in order to prevent costly redesigns of a target system. This article classifies the potential physical faults of a baseline TSV-based 3D NoC architecture by targeting Two-Dimensional (2D) NoC components and their inter-die connections. In this paper, Through-Silicon Via (TSV) issues, thermal concerns, and Single Event Effect (SEE) are investigated and categorized, in order to propose evaluation metrics for inspecting the resiliency of 3D NoC designs. A reliability analysis for major source of faults is reported in this article separately based on their Mean Time to Failure (MTTF). TSV failure probability induced by inductive and capacitive coupling is also discussed. Finally, the paper provides a formal reliability analysis on the aggregated faults that affect TSV. This formal analysis is critical for estimating the resiliency of different components in order to mitigate the redundancy cost of fault-tolerant design or to examine the efficiency of any proposed fault-tolerant methods for 3D NoC architectures.

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Section: Tsv Issuesmentioning

confidence: 99%

Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip

Eghbal

Bagherzadeh

Khayambashi

2015

IEEE Trans. Comput.

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“…In [5], [12], some layout guidelines have been proposed to optimize the stress-induced delay variation with regular TSV distribution topologies. The basic idea is to relocate the gates on the critical and near critical paths in mobility enhanced zone.…”

Section: Motivationmentioning

confidence: 99%

“…Xik Ij = IJ + llh-+j,k . Xik (12) Here If, I? +N2 and IJ are the original current sources connected to the nodes i, i + N 2 and j, respectively.…”

Section: Power and Stress Profiles Redistributionmentioning

confidence: 99%

“…In [5], a design flow is proposed to analyze timing variations due to TSV-induced stress. In [12], the authors demonstrated that the amount of path delay variations depends on the relative location of the gates to the TSVs, and proposed a set of layout guidelines to optimize delay variations. However, in these work, the TSVs were assumed to be regularly placed in advance.…”

Section: Introductionmentioning

confidence: 99%

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Stress-aware P/G TSV planning in 3D-ICs

Wang

Firouzi

Oboril

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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Power/Ground (P/G) Through-Silicon-Vias (TSVs) in the Power Distribution Network (PDN) of Three-Dimensional-Integrated Circuit (3D-IC) have a twofold impact on the delays of the surrounding gates. TSV fabrication causes thermal stress around TSVs, which results in significant carrier mobility variations in their vicinity. On the other hand, the insertion of PIG TSVs will change the voltage of each node in the power grid, which also impacts the delays of the connected gates.Thus, it is necessary to consider the combined effect on delay variation during the PIG TSV planning. In this work, we propose a methodology using Mixed-Integer-Bilinear-Programming (MIBLP) to optimize this delay variation by a refined PIG TSV allocation. Taking into account the impact of thermal stress as well as voltage drop on the circuit delay, we optimally plan the PIG TSVs to minimize the circuit delay for different keep-out zones (KOZs) and PDN pitches.

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“…Furthermore, we show that TSV-induced stress is biaxial in nature. Prior work in [5] uses a uniaxial model for TSV-stress, which incurs significant errors in mobility computations [10].…”

Section: Introductionmentioning

confidence: 99%

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

Marella

Sapatnekar

2015

IEEE Trans. VLSI Syst.

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In 3-D ICs, through silicon via (TSV)-induced thermal residual stress impacts several transistor electrical parameters-low-field mobility, saturation velocity, and threshold voltage. These thermal-stress related shifts are coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermallyinduced variations on circuit timing. A biaxial stress model is built, based on a superposition of 2-D axisymmetric and Boussinesq-type elasticity models. The computed stresses and strains are then employed to evaluate transistor mobility, saturation velocity, and threshold voltage. The electrical variations are translated into gate-level delay and leakage power calculations, which are then elevated to circuit-level analysis to thoroughly evaluate the variations in circuit performanceinduced by TSV stress. Index Terms-3-D IC, finite element method (FEM), static timing analysis, through silicon via (TSV).

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A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations

Cited by 15 publications

References 12 publications

Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip

Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip

Stress-aware P/G TSV planning in 3D-ICs

A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations

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