A highly stable SRAM memory cell with top-gated P-N drain poly-Si TFTs for 1.5 V operation

Hayashi, F.; Ohkubo, H.; Takahashi, Tomoko; Horiba, S.; Noda, K.; Uchida, Teiji; Shimizu, T.; Sugawara, N.; Kumashiro, S.

doi:10.1109/iedm.1996.553585

Cited by 22 publications

(8 citation statements)

References 1 publication

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“…It can also be used to meet the increasing demand for high-density multilayer three-dimensional (3-D) circuits. In fact, TFTs have already been used in 3-D circuits such as static random access memory components (SRAMs) and dynamic random access memories (DRAMs) [2]- [4]. However, performance of TFTs is limited by the large amount of randomly oriented grain boundaries (GBs) exist in the channel, which cause high threshold voltage (VT), low On-current (ION), gentle subthreshold slope and high leakage current [5], [6].…”

Section: Introductionmentioning

confidence: 99%

Effects of longitudinal and latitudinal grain boundaries on the performance of large-grain polysilicon MOSFET

Singh

Wang

Chan

2001

IEEE Electron Device Lett.

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The effects of longitudinal and latitudinal polysilicon grain boundaries on the performance metal oxide semiconductor field effect transistors (MOSFETs) fabricated on large-grain polysilicon-on-insulator (LPSOI) have been investigated. Unlike conventional thin-film-transistors (TFTs) with random grain distribution, MOSFETs fabricated on the LPSOI film contains the combination of only longitudinal or latitudinal grain boundaries. Longitudinal GBs parallel to the direction of current flow has smaller impact to the current flow, but provided extra leakage current that caused early device shortage, especially in wide devices. The latitudinal GBs perpendicular to the direction of current flow offered higher resistance to the inversion carriers thus causing lower current drive, higher threshold voltage, and gentler subthreshold slope. The result of the study can be used to optimize device design for high performance on MOSFETs on the LPSOI substrate.

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Section: Introductionmentioning

confidence: 99%

Effects of longitudinal and latitudinal grain boundaries on the performance of large-grain polysilicon MOSFET

Singh

Wang

Chan

2001

IEEE Electron Device Lett.

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“…Polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) have been studied for its potential using in the static random-access memory (SRAM) and as the integrating peripheral driving circuits in high-resolution active matrix liquid crystal displays due to their large mobility [1,2]. However, because of the defects in polySi TFT devices, some issues have to be resolved in comparison with the single crystalline transistors.…”

Section: Introductionmentioning

confidence: 99%

Formation of sub-micrometer polycrystalline-SiGe thin-film transistors by using a thinned channel layer

Juang¹,

Chang²,

Huang³

et al. 2010

Solid-State Electronics

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“…H IGH-PERFORMANCE low-temperature poly-Si thinfilm transistors (LTPS-TFTs) have been intensively investigated for the application of the active matrix liquid-phase crystal displays [1] and the three-dimensional (3-D) circuitintegration elements such as SRAMs and DRAMs [2], [3]. However, the poly-Si channel film would still have many grain boundaries which degrade the subthreshold swing S.S., threshold voltage V TH , and field-effect mobility µ FE and the results in a large operation voltage [4]- [6].…”

Section: Introductionmentioning

confidence: 99%

High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With $\hbox{TaN/HfO}_{2}$ Gate Stack Structure

Chao

et al. 2008

IEEE Electron Device Lett.

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In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateralcrystallization (MILC) channel layer and TaN/HfO 2 gate stack is demonstrated for the first time. The devices of low threshold voltage V TH ∼ 0.095 V, excellent subthreshold swing S.S. ∼ 83 mV/dec., and high field-effect mobility µ FE ∼ 240 cm 2 /V · s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO 2 gate dielectric with the effective oxide thickness of 5.12 nm. Index Terms-High-κ, low-temperature poly-Si thin-film transistor (LTPS-TFT), metal gate, metal-induced lateral crystallization (MILC).

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A highly stable SRAM memory cell with top-gated P-N drain poly-Si TFTs for 1.5 V operation

Cited by 22 publications

References 1 publication

Effects of longitudinal and latitudinal grain boundaries on the performance of large-grain polysilicon MOSFET

Effects of longitudinal and latitudinal grain boundaries on the performance of large-grain polysilicon MOSFET

Formation of sub-micrometer polycrystalline-SiGe thin-film transistors by using a thinned channel layer

High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With $\hbox{TaN/HfO}_{2}$ Gate Stack Structure

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