A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

Lue, Hang-Ting; Hsu, Tzu-Hsuan; Hsiao, Yi‐Hsuan; Hong, Shih-Ping; Wu, M. T.; Hsu, Fang-Hao; Lien, Nan-Chun; Wang, Szu-Yu; Hsieh, Jung-Yu; Yang, Lee‐Wei; Yang, Tahone; Chen, Kuang-Chao; Hsieh, Kuang-Yeu; Lu, Chih‐Yuan

doi:10.1109/vlsit.2010.5556199

Cited by 98 publications

(35 citation statements)

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“…A vertical gate (VG) approach has also been proposed [26][27][28], whereby the role of the control-gate and the channel can be reverted substantially with respect to vertical-channel structures.…”

Section: Vertical Gate-type Architecturesmentioning

confidence: 99%

3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

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Abstract:In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a "punch-and-plug" process-with gate-all-around (GAA) cell devices-against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.

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Section: Vertical Gate-type Architecturesmentioning

confidence: 99%

3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

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“…The main contributors have been Toshiba [1][2][3], Samsung [4][5][6][7], Macronix [8][9][10], Hynix [11][12][13], Micron [14] amongst the Memory companies. The main scope of 3D development was lowering the cost per bit and increase the chip density without shrinking the 2D lithography node.…”

Section: D Nand Architecturesmentioning

confidence: 99%

3D VG-Type NAND Flash Memories

Silvagni

2016

3D Flash Memories

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Solid State Disk applications have been the main drivers for the cost reduction of NAND Flash memory. Technology scaling limits have been almost reached and new directions were investigated for a decade. 3D NAND appeared as the most promising and short term viable solution to the scaling problem. 3D NAND offers the possibility to keep scaling memory density beyond 2D NAND 1z nm technology and opens new landscapes if the technology hurdles can be definitely overcome. Additionally Multi bit per cell technology is applicable to 3D NAND as well; therefore, the storage capacity growth trend is not going to meet the inflection point soon. Big Data storage demand remains certainly the driver for the rapidity of 3D NAND to become industry mainstream.With respect to the flat 2D NAND Flash, three-dimensional architectures demand a more challenging approach to deal with process, design architectures, parasitic effects, testing. At the time of writing this chapter, 3D technology is moving into production inside solid state storage solutions; however, those NAND chips aren't commercially available as raw components. 3D NAND chips are used by vertically integrated manufacturers and few partners to build the storage systems under a strict control on the usage. Technology solutions are still diversified among the few players in the 3D arena and no unique mainstream solution is emerged yet.In this chapter the principal architectural pieces of 3D NAND will be reviewed putting the focus on one of them: VG-Type, Vertical Gate 3D NAND.

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“…BiCS represent the concept of "bit-cost scalable" 3D NAND by means of a "one-etch" process that fabricate the whole multilayer 3D NAND at one step, thus providing the ideally minimal bit cost. After the pioneering work of "BiCS", various 3D NAND Flash architectures Jang et al 2009;Kim et al 2009a, b;Lue et al 2010) were proposed. The most popular architecture is the vertical channel (VC) NAND, such as P-BiCS ) and TCAT ).…”

Section: Brief Comparison Of Various 3d Nand Flash and A General Costmentioning

confidence: 99%

“…A suitable top SSL (String Selection) device arrangement is necessary to select/ decode the array. On the other hand, the vertical gate (VG) NAND (Kim et al 2009b;Lue et al 2010) has a very different array architecture. The device is a double-gate SONOS (or BE-SONOS) charge-trapping device.…”

Section: Brief Comparison Of Various 3d Nand Flash and A General Costmentioning

confidence: 99%

“…4.3. Finally, the photo overlay concerns in between the top SSL ), TCAT ), and VG (Kim et al 2009b;Lue et al 2010) , while VG may be scaled to 2X nm 5F 2 optimistically layout and hole further enlarge the cell size. A practical way of VC NAND is to design channel hole diameter (2 Â ONO + Si) in the range of 60-100 nm Jang et al 2009;Ishiduki et al 2009).…”

Section: Brief Comparison Of Various 3d Nand Flash and A General Costmentioning

confidence: 99%

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