A Highly Reliable Memory Cell Design Combined With Layout-Level Approach to Tolerant Single-Event Upsets

Qi, Chenze; Xiao, Liyi; Wang, Tianqi; Li, Jie; Li, Linzhe

doi:10.1109/tdmr.2016.2593590

Cited by 103 publications

(63 citation statements)

References 29 publications

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“…For investigating single-event effects in ICs, the three-dimensional mixed-mode (TCAD) simulation has been confirmed to be a practical means [3,13,14,15]. Thus, with using the Sentaurus TCAD, the TCAD models in this paper are calibrated from commercial 65 nm bulk CMOS process design kit (PDK) to make sure that the electrical characteristics between them are matched well.…”

Section: Simulation Results and Analysismentioning

confidence: 99%

“…The TCAD heavy ion physical model as the striking ion is employed with the charge track length and radius fixed at 10 um and 50 nm, respectively. Additionally, the ion striking at the center of the drain of the struck device, as well as the LET value being kept constant along the heavy ion track, is assumed in this paper [3]. Fig.…”

Section: Simulation Results and Analysismentioning

confidence: 99%

“…8(a) shows the TCAD model of the proposed RHEQ, where the x-z plain and the +y-axis are parallel and vertical to the surface of the cell, respectively. Meanwhile, the keywords θ and β are employed as the angle between the incident ion direction and the +y-axis and the angle between the projection direction of the incident ion in the x-z plane and the +x-axis with clockwise orientation, respectively [3]. The primary concerns in this paper are the SEU occurring on single node and SEMNUs caused by charge sharing among PMOSs in a single memory cell.…”

Section: Simulation Results and Analysismentioning

confidence: 99%

“…These surplus carriers might be gathered by the sensitive nodes through drift and diffusion as a consequence, resulting in a current (also known as voltage) perturbation at that node [2]. For memory cell, when the amplitude of the voltage perturbation is strong enough, the data stored might be altered temporarily, which may result in a SEU [3]. Moreover, with technology scaling, circuit nodal capacitances and supply voltage has been reduced radically, which makes static random access memory (SRAM) more vulnerable to SEU.…”

Section: Introductionmentioning

confidence: 99%

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A radiation harden enhanced Quatro (RHEQ) SRAM cell

Peng

Chen

Zhang

et al. 2017

IEICE Electron. Express

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This paper intends to present a novel radiation-hardened SRAM cell by using the PMOS transistors stacked (each PMOS is split into two same sizes) and changing the inner topological structure on basis of the Quatro-10T. Combined with layout-level optimization design, the 3-D TCAD mixed-mode simulation results show that the novel design has a great single event upset (SEU) immune. Simultaneously, it is found to be tolerant of partial single-event multiple-node upsets (SEMNUs) due to the charge sharing among off-PMOS transistors. In addition, compared with the Quatro-10T, our proposed structure exhibits larger static noise margin (SNM) as well as lower power consumption in 65 nm COMS technology.

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Section: Simulation Results and Analysismentioning

confidence: 99%

Section: Simulation Results and Analysismentioning

confidence: 99%

Section: Simulation Results and Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A radiation harden enhanced Quatro (RHEQ) SRAM cell

Peng

Chen

Zhang

et al. 2017

IEICE Electron. Express

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“…The 14T cell achieves better electrical performances and lower area cost, but the critical charge is by no means preferable to the 18T cell. Along came some other designs [7,8,9], however, the SEU hardening capabilities of these cells are not satisfactory enough.…”

Section: Introductionmentioning

confidence: 99%

A novel SEU hardened SRAM bit-cell design

Yang²,

Zhang

et al. 2017

IEICE Electron. Express

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An improved single event upset (SEU) tolerant static random access memory (SRAM) bit-cell with differential read and write capability is proposed. SPICE simulation suggests a more than 1000 times improvement of the critical charge over the standard 6T SRAM cell. With the SEU robustness greatly enhanced at low area and electrical performance costs, the proposed cell is well suited to harsh radiation environment applications such as aerospace and high energy physics.

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