A highly integrated biomedical multiprocessor SoC design for a wireless bedside monitoring system

Lin, Kuen Chih; Liao, Jui Chieh; Fang, Wai-Chi

doi:10.1109/iscas.2014.6865404

Cited by 6 publications

(3 citation statements)

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“…This work employed the state-of-the-art 65-nm at 1 KHz and resulted in the smallest possible area among all the other designs (0.03416 mm 2 ). A total power of 0.614 mW was consumed and found to be much better compared to most of the designs ( [8], [9], and [10]). Furthermore, the performance of the proposed algorithm was evaluated on the Physionet QT database [14] using 20 single-lead ECG records sampled at 250 Hz.…”

Section: Performance and Resultsmentioning

confidence: 94%

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A 65-nm low power ECG feature extraction system

Bayasi

Tekeste

Saleh

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a real-time adaptive ECG detection and delineation algorithm alongside an architecture based on time-domain signal processing of the ECG signal. The algorithm is enhanced to detect large number of different P-QRS-T waveform morphologies using adaptive search windows and adaptive threshold levels. The proposed architecture has been implemented in the state-of-the-art 65-nm CMOS technology. It occupied 0.03416 mm2 area and consumed 0.614 mW power. Furthermore, the non-complex nature of the architecture resulted with a realization using smaller number of computation and higher performance. The design of the QRS detector was tested on ECG records obtained from the Physionet QT database and achieved a sensitivity of Se =99.83% and a positive predictivity of P + = 98.65%. Similarly, the mean error values of the T peak, T offset, P peak and P offset were found to be -1.367, 6.36, 5.5 and -2.59 milliseconds, respectively, using the same database. The small area, low power, and high performance of our architecture makes it suitable for inclusion in System On Chips (SOCs) targeting wearable mobile medical devices.Index Terms-ECG signal, QRS detection, T-and P-wave delineation, ASIC design, hardware implementation, adaptive technique, low power.978-1-4799-8391-9/15/$31.00 ©2015 IEEE

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Section: Performance and Resultsmentioning

confidence: 94%

“…Another ECG monitoring 0.18 μm SoC was designed by Yan et al in [8] for a low power wearable cardiac devices. Similarly, the authors in [9], [10], and [11] presented highly integrated SoC designs for configurable and low power ECG monitoring and diagnosis systems and devices.…”

Section: Introductionmentioning

confidence: 99%

A 65-nm low power ECG feature extraction system

Bayasi

Tekeste

Saleh

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…To overcome some of these limitations, an emerging trend has been the use of (mechanically and electrically) integrated designs via microchips. Microchip technologies hold several key advantages, including a small footprint, low power consumption, better timing synchronization between fNIRS and EEG measurements, and potentially improved signal quality with reduced noise and crosstalk [ 32 , 72 ]. Several attempts at a microchip-based, wearable, integrated EEG–fNIRS system have been made in the last ten years [ 44 , 45 , 46 , 47 ].…”

Section: Discussionmentioning

confidence: 99%

Wearable, Integrated EEG–fNIRS Technologies: A Review

Uchitel

Vidal-Rosas

Cooper

et al. 2021

Sensors

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There has been considerable interest in applying electroencephalography (EEG) and functional near-infrared spectroscopy (fNIRS) simultaneously for multimodal assessment of brain function. EEG–fNIRS can provide a comprehensive picture of brain electrical and hemodynamic function and has been applied across various fields of brain science. The development of wearable, mechanically and electrically integrated EEG–fNIRS technology is a critical next step in the evolution of this field. A suitable system design could significantly increase the data/image quality, the wearability, patient/subject comfort, and capability for long-term monitoring. Here, we present a concise, yet comprehensive, review of the progress that has been made toward achieving a wearable, integrated EEG–fNIRS system. Significant marks of progress include the development of both discrete component-based and microchip-based EEG–fNIRS technologies; modular systems; miniaturized, lightweight form factors; wireless capabilities; and shared analogue-to-digital converter (ADC) architecture between fNIRS and EEG data acquisitions. In describing the attributes, advantages, and disadvantages of current technologies, this review aims to provide a roadmap toward the next generation of wearable, integrated EEG–fNIRS systems.

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Advancements in Measuring Cognition Using EEG and fNIRS

Chandra

Choudhury

2023

Handbook of Metrology and Applications

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A highly integrated biomedical multiprocessor SoC design for a wireless bedside monitoring system

Cited by 6 publications

References 10 publications

A 65-nm low power ECG feature extraction system

A 65-nm low power ECG feature extraction system

Wearable, Integrated EEG–fNIRS Technologies: A Review

Advancements in Measuring Cognition Using EEG and fNIRS

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