A Highly Efficient Heterogeneous Processor for SAR Imaging

Abstract

The expansion and improvement of synthetic aperture radar (SAR) technology have greatly enhanced its practicality. SAR imaging requires real-time processing with limited power consumption for large input images. Designing a specific heterogeneous array processor is an effective approach to meet the power consumption constraints and real-time processing requirements of an application system. In this paper, taking a commonly used algorithm for SAR imaging—the chirp scaling algorithm (CSA)—as an example, the characteristics of each calculation stage in the SAR imaging process is analyzed, and the data flow model of SAR imaging is extracted. A heterogeneous array architecture for SAR imaging that effectively supports Fast Fourier Transformation/Inverse Fast Fourier Transform (FFT/IFFT) and phase compensation operations is proposed. First, a heterogeneous array architecture consisting of fixed-point PE units and floating-point FPE units, which are respectively proposed for the FFT/IFFT and phase compensation operations, increasing energy efficiency by 50% compared with the architecture using floating-point units. Second, data cross-placement and simultaneous access strategies are proposed to support the intra-block parallel processing of SAR block imaging, achieving up to 115.2 GOPS throughput. Third, a resource management strategy for heterogeneous computing arrays is designed, which supports the pipeline processing of FFT/IFFT and phase compensation operation, improving PE utilization by a factor of 1.82 and increasing energy efficiency by a factor of 1.5. Implemented in 65-nm technology, the experimental results show that the processor can achieve energy efficiency of up to 254 GOPS/W. The imaging fidelity and accuracy of the proposed processor were verified by evaluating the image quality of the actual scene.

InSAR Signal and Data Processing

“…The eighth article [ 8 ], “ScanSAR Interferometry of the Gaofen-3 Satellite with Unsynchronized Repeat-Pass Images”, discusses interferometric analysis and processing methods for GaoFen-3 images in ScanSAR mode. The ninth paper [ 9 ], “A Highly Efficient Heterogeneous Processor for SAR Imaging”, concerns the hardware design of a SAR signal processor consisting of two heterogeneous arrays that provide 115.2 GOPS throughput. In the tenth paper [ 10 ], “Monitoring the Land Subsidence Area in a Coastal Urban Area with InSAR and GNSS”, 34 scenes of Sentinel-1A SAR images are used for SBAS and PS processing to obtain the surface deformation field of a large region spanning the Shenzhen, China, and Hong Kong Special Administrative Regions.…”

FPGA Implementation of the Chirp-Scaling Algorithm for Real-Time Synthetic Aperture Radar Imaging

“…Operations for SAR imaging mainly include the fast Fourier transform (FFT), inverse fast Fourier transform (IFFT), phase compensation, interpolation, etc., and the computational complexity of these operations is very high. Therefore, real-time SAR imaging necessitates accelerating these operations on various computing platforms, such as the central processing unit (CPU), the graphic processing unit (GPU), the field-programmable gate array (FPGA), and application-specific integrated circuits (ASICs) [ 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 ]. CPU and GPU provide high flexibility for software through various instructions and show high performance in single and parallel processing, respectively.…”

“…Wang et al proposed a heterogeneous processor consisting of fixed-point PE units and floating-point PE units. It acquired a 32,768 × 32,768-pixel image in 32.9 s at a speed of 200 MHz [ 16 ]. Li et al proposed a method that employs single-instruction, multiple-data (SIMD) instructions and open multiprocessing (OpenMP) technology on multicore SIMD CPU to realize parallel optimization on CSA [ 17 ].…”

Hardware accelerated range Doppler algorithm for SAR data processing using Zynq processor

“…The radix 2 k algorithm was implemented in the XC6VCX240T FPGA board using an 18-bit pipeline algorithm achieving 47.3 dB signal to quantization noise ratio. Wang et al (2019) addressed the constraints of power consumption in real-time SAR processing and presented a heterogeneous architecture of fixed point and floating point units supporting fast FFT/inverse FFT (IFFT). An embedded architecture of the SAR processor for frequencymodulated continuous-wave RADAR application was presented using Zynq 7000 board by Wagner et al (2018).…”