A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications

Expanding role of predictive TCAD in advanced technology development

“…As illustrated in Figure 1, these innovations include channel mobility enhancement by process-induced strain [4][5][6][7][8][9][10], Tinv scaling with gate tunneling reduction by high-K/metal gate [11][12][13], and electrostatic control improvement by transition from planar single gate to 3D FinFET/Multi-Gate FET (MUGFET) structures [14][15][16][17][18][19][20]. These transistor performance enhancements have also increased process complexity significantly.…”

“…Fig. 4 Hole mobility polar plots for (110)/ [1][2][3][4][5][6][7][8][9][10] in response to three stress components [30] From planar to FinFET, another change is inversion layer quantization. When the fin width is scaled down, the inversion layer quantization deviates from triangular well approximation and gets into volume inversion determined by geometrical confinement.…”

Low-on-resistance strain-controlled LDMOS transistors for 0.25-μm power ICs

“…This resistance component is the same as the channel resistance in a usual NMOS transistor. Applying tensile stress to the channel region using an etch-stop SiN layer is often utilized for nanoscale NMOS transistors [4]. However, this technique is not suitable for LDMOS transistors because it will produce compressive stress in the offset-drain region and increase R on .…”

“…However, they currently have difficulty in integrating digital circuits and less dependability and rather a higher cost than Si. On the other hand, the locally strained Si technique is commonly introduced to nanoscale CMOS transistors for achieving higher drive current [3,4], which means a lower on-state resistance. A globally strained LDMOS transistor using a strained-Si/SiGe substrate [5] and a locally strained power MOS transistor [6] have been proposed.…”

Effects of Channel Width on Stress Enhancement for Damascene-Gate nFETs With Top-Cut Tensile-Stress Liner

“…Moreover, enhancement effects of L gate and W ch on the channel stress have been precisely evaluated using stress simulation and UV-Raman spectroscopy for damascene-gate pFETs with embedded SiGe and top-cut compressive-stress SiN liner [3]- [6]. However, the behavior of the channel stress in the narrow W ch is not clear for damascene-gate nFETs with top-cut tensilestress SiN liner (t-SL) yet, as compared with conventional gatefirst nFETs [7], [8]. Manuscript In this letter, the effects of W ch on drivability enhancement are studied for the damascene-gate nFETs with the top-cut t-SL using 3-D stress simulations and demonstrations.…”