A high yield 12-bit 250-MS/s CMOS D/A converter

A 12-Bit 1-Gsample/s Nyquist Current-Steering DAC in 0.35 µm CMOS for Wireless Transmitter

“…A new swing-reduced-device (SRD) circuit is designed (shown in Figure 11(b)). The latch circuit complementary output levels and non-symmetrical cross point are designed to minimize glitches [13]. The waveforms of the different nodes are shown in Figure 11(c) without SRD circuit and Figure 11(d) with SRD circuit.…”

“…However, this is unfeasible in practice due to the large area and delay that the thermometer decoder would exhibit. The minimization of the glitch energy is then done in circuit level design and layout of the switch and latch array and current source cell [13].The optimum segmentation is workout 75% in [10,12] so we have used this segmentation to achieve the best performance in high-speed design. Thus we consider 9-bit as thermometer-coded and 3-bit as binary-weighted.…”

A 1.5-v 14-bit 100-MS/s self-calibrated DAC

“…Based on a model given in [15], to achieve integral nonlinearity (INL) and differential nonlinearity (DNL) of less than 0.5 LSB for a 14-bit DAC at the 99% yield level without any trimming or calibration requires a relative standard deviation of the unit current sources, , of less than 0.22% to overcome the effects of random process variations in addition to a layout that is insensitive to gradient effects. With this , the minimum gate area for the current source transistors can be determined [6], [7], [10]. In the specific 0.13-m CMOS process used in our implementation, the total gate area , without calibration, would need to be about 1.5 mm to overcome the effects of random current source mismatch.…”

“…A DAC contains multiple copies of these current source cells and they are typically judiciously laid out in geometric arrays. Without any trimming or calibration, large-area current sources must be used to overcome the detrimental effects of random mismatch on yield [6], [7], [10]. For a high-resolution DAC, the current source array usually comprises several square millimeters of area.…”

Design techniques for high-performance current-steering digital-to-analog converters

“…Generally, random variations of devices are assumed to be uncorrected and follow the Gaussion distribution. If the designed value of unit current sources is I, when only random mismatch is present, the actual current provided by the jth (1< j <N) unit current source can be expressed as [10], [11]. An important conclusion drawn from this expression is that the current variation is inversely proportional to the gate area of the transistor.…”