A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing

Yang, Yao-Chang; Lin, Chun-Liang; Chang, Hsui-Cheng; Su, Ching-Lung; Guo, Jiun-In

doi:10.1109/icme.2006.262510

Cited by 14 publications

(5 citation statements)

References 4 publications

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“…Techniques to reduce the latency and data dependency of CABAD have been widely discussed in the literature and they follow five basic approaches: pipeline; contexts pre-fetching and cache; elimination of renormalization loop; parallel decoding engines; and memory organization. The pipeline strategy is used in [4] to increase the bins/cycle rate. An alternative to solve the latency of renormalization process is presented in [5].…”

Section: Related Workmentioning

confidence: 99%

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Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis

Deprá

Bampi

2011

VLSI-SoC: Technologies for Systems Integration

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The design and implementation of a hardware accelerator dedicated to Binary Arithmetic Decoding Engine (BADE) is presented. This is the main module of the Context-Adaptive Binary Arithmetic Decoder (CABAD), as used in the H.264/AVC on-chip video decoders. We propose and implement a new approach for accelerating the decoding hardware of the significance map by providing the correct context for the regular hardware engine of the (CABAD). The design development was based on a large set of software experiments, which aimed at exploiting the characteristic behavior of the bitstream during decoding. The analysis gave new insights to propose a new hardware architecture to improve throughput of regular engines for significance map with low silicon area overhead. The proposed solution was described in VHDL and synthesized to standard cells in IBM 0.18 μm CMOS process. The results show that the developed architecture reaches 187 MHz with a non optimized physical synthesis.

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Section: Related Workmentioning

confidence: 99%

“…High efficiency in the decoding process using pre-fetching and cache contexts is discussed in [6] and [9], respectively. Memory optimization and reorganization are addressed in [4].…”

Section: Related Workmentioning

confidence: 99%

Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis

Deprá

Bampi

2011

VLSI-SoC: Technologies for Systems Integration

View full text Add to dashboard Cite

show abstract

“…The pipeline strategy is employed by [14] for increasing rate of bins/cycle. An alternative to solve the latency of renormalization process is presented in [2].…”

Section: Related Workmentioning

confidence: 99%

“…High efficiency of decoding process employing pre-fetching and cache contexts is discussed in [15] and [16], respectively. The memory optimization and reorganization are addressed in [14].…”

Section: Related Workmentioning

confidence: 99%

A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis

Deprá

Rosa

Bampi

2008

Proceedings of the 21st Annual Symposium on Integrated Circuits and System Design

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This paper presents the design and implementation of a dedicated hardware architecture for binary arithmetic decoder (BAD) engines of CABAD, as defined in the H.264/AVC video compression standard. The BAD is the most important CABAD process, which is the main entropy encoding method defined by the H.264/AVC standard. The BAD is composed by tree engines: Regular, Bypass and Terminate. A large set of software experiments was made to profile each engine. Based on bitstream flow analysis a new dedicated hardware architecture was proposed to improve the hardware efficiency of BAD engines. The proposed solution was described in VHDL and synthesized to a Xilinx Virtex2-Pro FPGA. The results show that the developed architecture reaches 103 MHz, and delivers up to 4 bins per cycle in bypass engines, against 2 bins per cycle as exposed in the literature.

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“…Accordingly, we propose a new parallelism processing approach and an additional prediction method. [5] one-bin yes no no [7] multi-bin no yes no [8] two-bin yes yes no [9] one-bin yes yes no [10] multi-bin no yes no [11] two-bin unknown yes yes [13] one-bin yes yes yes [14] two-bin yes yes yes…”

Section: Introductionmentioning

confidence: 99%

A very high throughput fully hardwired CABAC decoder

Chang

Lin

2009

2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

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Context-based Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC can achieve high compression ratio at the expense of high computational complexity. We have previously proposed a fully hardwired CABAC decoder that supports real-time QFHD (4x1080HD) decoding at maximum bit rate of 80 Mbps. For higher end applications, we analyze the bin distribution of each Syntax Element (SE) type and the performance of our previous work. The analysis results show that mvd SEs account for significant amount of bins and GetNeighbor (GN) process degrades the utilization of Arithmetic Engine (AE). Therefore, we propose three methods to speed up mvd decoding and increase AE utilization. For mvd SEs, we employ a Two-Bin Arithmetic Engine (TBAE) to decode two mvd bins per cycle. To increase AE utilization, we reduce the cycle-count of the GN process and propose a prediction method to perform AE and GN in parallel. Experimental results show that our new CABAC decoder gives 45% throughput improvement and is capable of decoding QFHD video at maximum bit rate of 221 Mbps when running at 238 MHz.

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A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing

Cited by 14 publications

References 4 publications

Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis

Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis

A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis

A very high throughput fully hardwired CABAC decoder

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