A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis

Abstract

This paper presents the design and implementation of a dedicated hardware architecture for binary arithmetic decoder (BAD) engines of CABAD, as defined in the H.264/AVC video compression standard. The BAD is the most important CABAD process, which is the main entropy encoding method defined by the H.264/AVC standard. The BAD is composed by tree engines: Regular, Bypass and Terminate. A large set of software experiments was made to profile each engine. Based on bitstream flow analysis a new dedicated hardware architecture was proposed to improve the hardware efficiency of BAD engines. The proposed solution was described in VHDL and synthesized to a Xilinx Virtex2-Pro FPGA. The results show that the developed architecture reaches 103 MHz, and delivers up to 4 bins per cycle in bypass engines, against 2 bins per cycle as exposed in the literature.

Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis

“…A large number of test-benches were developed and run to evaluate the performance of our architecture with data extracted from the reference software during the decoding process of the 440 digital video sequences listed in Section 4. For these video test-benches we observed that the two main approaches adopted can improve the throughput when compared to previous works presented in [6] and [12]. So, the potential gain for the four Bypass engines (4 BYPASS) and for the specialized context selection for significance map in regular engines (SP SIGMAP) were analyzed for each different resolution of the video sequences tested.…”

“…It compares the solutions with two and four decoder bypass engines in the architecture and our design. The results in Table 3 indicate that the increase in the hardware costs is around 2.4% for our design and the maximum frequency decreases 1.7%, both when compared to the design proposed in [12]. A large number of test-benches were developed and run to evaluate the performance of our architecture with data extracted from the reference software during the decoding process of the 440 digital video sequences listed in Section 4.…”

“…Our design is based on the work presented in [12] which applies multiple parallel engines for speculative execution. In this work we include few extensions mainly in the regular branch.…”

CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey

“…However, it results in an extra cost of the register bank. The architectures [10][11] [12][13] [14] are based on the same concept, but after some specific extensions are capable to en-/decode HD video. In [15] sixteen cascaded regular decoding units are used for more speed up for frequent SEs.…”

“…In the parallel approach the number of bins/cycle fluctuates between a certain maximum and minimum, as it depends on the type of SE. It may result in 2, 3 or even 4 bins/cycle if supported by the architecture as in [12] [14]. In the purely pipeline approach the throughput never goes above more than 1 bin/cycle, but independent of SEs it remains at 1 or close to 1 bin/cycle.…”