A High-Throughput Hardware Architecture for AV1 Non-Directional Intra Modes

Corrêa, Marcel; Waskow, Bianca; Goebel, Jones; Palomino, Daniel; Corrêa, Guilherme; Agostini, Luciano

doi:10.1109/tcsi.2020.2973031

Cited by 13 publications

(5 citation statements)

References 30 publications

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“…The parallelism strategy allowed the processing of one block row/column per clock cycle, thus, the number of cycles depends on the width or height of the block, whichever is the largest. Similarly, in [53] a non-directional intra prediction module for the encoder capable of processing 11 non-directional modes was presented. A throughput of UHD 4K at 30 fps was reported for both architectures.…”

Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

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This article presents an extensive review of the state-of-the-art system-level solutions featuring complexity reduction and/or dedicated hardware designs for the AV1 and VVC video coding formats. These formats introduced several novel coding techniques compared to their predecessors to improve the coding efficiency at the cost of a significant computational cost. In this article, we discuss the main novelties of AV1 and VVC in each coding module, including block partitioning, intra and inter prediction, transform, entropy coding, and in-loop filters. Then, we present the main published works focusing on complexity reduction and hardware designs for AV1 and VVC. Most of the complexity reduction solutions target the complex and flexible block partitioning structures of these encoders to provide a better tradeoff between coding efficiency and complexity reduction whereas the hardware designs focus on the challenge of implementing the new coding tools to attend real-time processing of high-definition videos. Even with the presented works reaching impressive results, these research fields remain opened for innovative contributions, as discussed in this article.

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Section: B Dedicated Hardware Designs For Av1mentioning

confidence: 99%

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Corrêa

Saldanha

Borges

et al. 2021

IEEE Open J. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…AV1 also introduced a chrominance-from-luminance (CfL) mode, which can predict chrominance samples from reconstructed luminance samples. Currently, a limited number of works in the literature present hardware architectures targeting this module for AV1 [46], [47] and [48].…”

Section: Intra-frame Predictionmentioning

confidence: 99%

“…The proposed architecture can process 1080p resolution at 60fps with a power consumption of 382.08mW. On the other hand, [47] proposes a hardware architecture focusing on the non-directional modes, achieving a high throughput for UHD 4K video sequences, and supporting all 19 available block sizes for this module. This solution processes up to 30 fps at 4K resolution, with a power consumption of 65.5mW.…”

Section: Intra-frame Predictionmentioning

confidence: 99%

Modern Video Coding: Methods, Challenges and Systems

Palau

Silveira

Domanski

et al. 2021

JICS

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With the increasing demand for digital video applications in our daily lives, video coding and decoding become critical tasks that must be supported by several types of devices and systems. This paper presents a discussion of the main challenges to design dedicated hardware architectures based on modern hybrid video coding formats, such as the High Efficiency Video Coding (HEVC), the AOMedia Video 1 (AV1) and the Versatile Video Coding (VVC). The paper discusses eachstep of the hybrid video coding process, highlighting the main challenges for each codec and discussing the main hardware solutions published in the literature. The discussions presented in the paper show that there are still many challenges to be overcome and open research opportunities, especially for the AV1 and VVC codecs. Most of these challenges are related to the high throughput required for processing high and ultrahigh resolution videos in real time and to energy constraints of multimedia-capable devices.

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“…But even with this relevance, there are still a few published works for AV1 hardware implementations. For the intra-frame prediction step, there are only six works: [16], [17], [18], [19], [20] and [21]. For the inter-frame prediction step, four works were identified: [22], [23], [24] and [25].…”

Section: Introductionmentioning

confidence: 99%

High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters

Palau

Penny

Viana

et al. 2023

JICS

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This paper presents a high-throughput hardware design for the Switchable Loop Restoration Filter (SLRF) of the AOM Video 1 (AV1) video format. This hardware includes the two filters defined at the AV1 SLRF: the Separable Symmetric Normalized Wiener Filter (SSNWF) and the Dual Self- Guided Filter (DSGF). The SLRF is the last step in the AV1 loop restoration filters, and it is used to attenuate blurring artifacts, improving the subjective video quality and the coding efficiency. The designed hardware targeted the AV1 decoderand is able to process up to 4K Ultra-High Definition (4K UHD) videos (with 3840x2160 pixels) at 60 frames per second (fps) in real-time. In order to cover different scenarios, two other target throughputs were also evaluated: 4K UHD at 30fps and Full HD (FHD) (with 1920x1080 pixels) at 30fps. The architectures were synthesized for standard cells using the 40 nm TSMC library. The SSNWF and DSGF architectures used 37.38 Kgates and 177.58 kgates in all evaluated scenarios. Depending on the evaluated scenario, the SSNWF power dissipation varied from 8.25mWto 26.95mWand the DSGF power varied from 57.19 mW to 115.02 mW. This is the first paper in the literature presenting a hardware design for the AV1 SLRF with its two filters.

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A High-Throughput Hardware Architecture for AV1 Non-Directional Intra Modes

Cited by 13 publications

References 30 publications

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

Modern Video Coding: Methods, Challenges and Systems

High-Throughput Hardware Design for the AV1 Decoder Switchable Loop Restoration Filters

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