A high throughput architecture for a low complexity soft-output demapping algorithm

Abstract

Abstract. Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.

Implementação e análise de técnica para estimação de SNR baseado em Deep Learning

“…O demapeamento QAM emprega o processo de decisão suave (soft-decision), para obter os valores de LLR (Log-Likelihood Ratio) associados a cada símbolo QAM demapeado. Uma versão de baixa complexidade do cálculo de LLR, baseado em [9], foi implementada visando reduzir o custo computacional.…”

Physical Layer Latency Management Mechanisms: A Study for Millimeter-Wave Wi-Fi

“…In the studied demapper implementations, only the throughput delay is considered since it is the main performance metric noted in [36][37][38]. The delay manifests itself as the time between the processing of consecutive input symbols.…”

Efficient quantization and fixed-point representation for MIMO turbo-detection and turbo-demapping

“…[ 10]. In fact, the multiplication of these two 16-b values results in 32-b product value that can be represented in Q [ 15] . [ 17].…”

“…In [14], the quantization and fixedpoint representation of few parameters of SISO demapper algorithm have been presented without showing their effect on the demapper performance. In [15], the authors proposed an architecture that supports only 16-QAM modulation scheme. The quantization of input and output has been only provided without mentioning the fixedpoint representation.…”