A High Throughput and Energy-Efficient Retina-Inspired Tone Mapping Processor

Liu, Huan; Xiang, Xiaoqiang; Xie, Yi; Li, Yongjie; Yan, Bo; Zhou, Jun

doi:10.1109/fccm.2019.00062

Cited by 3 publications

(1 citation statement)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Liu et al reported a retina-inspired [156] tone mapping algorithm by implementing horizontal and bipolar cell stages on a Xilinx Virtex 7 FPGA [39]. The design operated at 150 MHz consumed 819 mW power while processing a 1024 × 768 image which corresponds to an energy efficiency of 544453 pixels/mW/s.…”

Section: Field Programmable Gate Arraymentioning

confidence: 99%

Real-time Tone Mapping: A State of the Art Report

Ou,

Ambalathankandy,

Ikebe

et al. 2020

Preprint

View full text Add to dashboard Cite

The rising demand for high quality display has ensued active research in high dynamic range (HDR) imaging, which has the potential to replace the standard dynamic range imaging. This is due to HDR's features like accurate reproducibility of a scene with its entire spectrum of visible lighting and color depth. But this capability comes with expensive capture, display, storage and distribution resource requirements. Also, display of HDR images/video content on an ordinary display device with limited dynamic range requires some form of adaptation. Many adaptation algorithms, widely known as tone mapping operators, have been studied and proposed in the last few decades. In this state of the art report, we present a comprehensive survey of 50+ tone mapping algorithms that have been implemented on hardware for acceleration and real-time performance. These algorithms have been adapted or redesigned to make them hardware-friendly. This effort leads to various design challenges that are encountered during the hardware development. Any real-time application poses strict timing constraints which requires time exact processing of the algorithm. Also, most of the embedded systems would have limited system resources in terms of battery, computational power and memory resources. These design challenges require novel solutions, and in this report we focus on these issues.In this we survey will discuss those tonemap algorithms which have been implemented on GPU [1-10], FPGA , and ASIC [42][43][44][45][46][47][48][49][50][51][52][53] in terms of their hardware specifications and performance. Output image quality is an important metric for tonemap algorithms. From our literature survey we found that, various objective quality metrics have been used to demonstrate the functionality of adapting the algorithm on hardware platform. We have compiled and studied all the metrics used in this survey [54][55][56][57][58][59][60][61][62][63][64][65][66][67]. Finally, in this report we demonstrate the link between hardware cost and image quality thereby illustrating the underlying trade-off. This report concludes with a discussion on the general future research directions based-on various hardware design/implementation bottlenecks which will be useful for the research community.

show abstract

Section: Field Programmable Gate Arraymentioning

confidence: 99%