[Invited Paper] HDR Tone mapping: System Implementations and Benchmarking

Ikebe, Masayuki; Ambalathankandy, Prasoon; Ou, Yafei

doi:10.3169/mta.10.27

Cited by 1 publication

(1 citation statement)

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“…Hardware processing using an fieldprogrammable gate array (FPGA) is promising for such applications. However, most of the existing FPGA implementations of HDR synthesis adopted the two-stage approach using image composition and tone mapping [2]- [7], which is computationally complex and requires parameter tuning for specific camera devices. thesis based on the simplified Mertens' method has been proposed in [8], the implementation depends on external memory (DRAM) for buffering image frames, which inevitably results in high latency and requires additional implementation area and costs.…”

Section: Introductionmentioning

confidence: 99%

Pipelined ADPCM Compression for HDR Synthesis on an FPGA

NISHIMURA,

MANABE,

SHIBATA

2024

IEICE Trans. Fundamentals

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This paper presents an FPGA implementation of real-time high dynamic range (HDR) synthesis, which expresses a wide dynamic range by combining multiple images with different exposures using image pyramids. We have implemented a pipeline that performs streaming processing on images without using external memory. However, implementation for high-resolution images has been difficult due to large memory usage for line buffers. Therefore, we propose an image compression algorithm based on adaptive differential pulse code modulation (ADPCM). Compression modules based on the algorithm can be easily integrated into the pipeline. When the image resolution is 4K and the pyramid depth is 7, memory usage can be halved from 168.48% to 84.32% by introducing the compression modules, resulting in better quality.

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Section: Introductionmentioning

confidence: 99%