A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI

Bassi, Matteo; Radice, Francesco; Bruccoleri, Melchiorre; Erba, Simone; Mazzanti, Andrea

doi:10.1109/jssc.2016.2598223

Cited by 39 publications

(5 citation statements)

References 25 publications

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“…where R is a termination impedance at I/O pad and internal circuit and is normally 50 . In this work, the diode with C ESD of 380 fF is adopted to meet the general ESD protection requirement of > 2-kV in human body model [16].…”

Section: Circuit Designmentioning

confidence: 99%

Compact and Broadband ESD Protection I/O Pad Using Pad-Stacked Inductor

et al. 2023

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In this paper, a compact and broadband electrostatic discharge (ESD) protection input/output (I/O) pad for high-speed interfaces is designed and miniaturized using a pad-stacked inductor in a 28-nm CMOS technology. A π-diode with a single inductor is adopted to compensate for the parasitic capacitance and extend the bandwidth of ESD-protected I/O pad. To minimize the increase of the chip area by the inductor, the pad-stacked inductor is proposed, where the inductor is placed below I/O pad. The eddy current, then, is induced in the I/O pad by time-varying magnetic field by the inductor, degrading the performance of the inductor, such as the reduced inductance, increased resistance and capacitance. These effects are thoroughly investigated using the developed equivalent circuit model which is also utilized to design the pad-stacked inductor. The compact and broadband π-diode with the reduced eddy current is then designed by the proper selection of the inductor layer and a patterned I/O pad. Measurement of the designed π-diode with the pad-stacked inductor exhibits broadband impedance match and insertion loss, that is, a return loss better than 10 dB up to 26.5 GHz and a 3-dB bandwidth as large as 22.9 GHz. The chip area of the π-diode remains the same as that of the I/O pad thanks to the proposed pad-stacked inductor. Therefore, the designed π-diode can be applied for the compact high-speed I/O interface circuits.INDEX TERMS Broadband, electrostatic discharge, high-speed, input/output pad.

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Section: Circuit Designmentioning

confidence: 99%

Compact and Broadband ESD Protection I/O Pad Using Pad-Stacked Inductor

et al. 2023

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“…An SST driver provides a high-speed and lowpower solution for SERDES signal transmitting. However, compared to the current mode logic (CML) with a 50-ohm resistor as the output load, the output impedance and linearity of the SST driver with the transistor load are more easily affected by the output voltage [23]- [25]. As shown in Fig.…”

Section: Nonlinearity Analysis Of An Sst Drivermentioning

confidence: 99%

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

Ding

Jin

Zhou

2022

IEICE Trans. Fundamentals

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This brief presents A 16/32 Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude linearity of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed to implement the proposed architecture. The proposed transmitter is manufactured in a 22nm FD-SOI process. The linearity calibration loop reduces the peak INL errors of the transmitter by 50%, and the RLM rises from 92.4% to 98.5% when the transmitter is in PAM4 mode. The chip area of the transmitter is 0.067 mm 2 , while the proposed linearity enhanced part is 0.05×0.02 mm 2 and the total power consumption is 64.6 mW with a 1.1 V power supply. The linearity calibration loop can be detached from the circuit without consuming extra power.

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“…The ADC-based PAM4 receiver was became an attractive solution, as the power of the DSP can be reduced by scaling the CMOS process. To support PAM4 transmission, voltage-mode transmitters [8], current-mode transmitters [9]- [12], and a hybrid transmitter [13] that combines a voltage-mode driver with an auxiliary current-injection driver have been studied. The voltage-mode transmitters are predominantly used in low-power mobile applications, owing to their low static current consumption.…”

Section: Introductionmentioning

confidence: 99%

A 16/32 Gb/s Dual-Mode NRZ/PAM4 Voltage-Mode Transmitter With 2-Tap FFE

et al. 2022

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This paper describes a voltage-mode transmitter that supports both non-return-to-zero (NRZ) and four-level pulse amplitude modulation (PAM4) signal transmission. A 2-tap feed-forward equalizer (FFE) is implemented with PAM4 equalization logic consisting of three stages of logic gates and two separated voltage-mode drivers for multi-level generation. Equalization is performed in both the NRZ and PAM4 signal transmission modes. A prototype chip is fabricated using a 28-nm CMOS process. When transmitting 500-mVp-p signals using the proposed transmitter, 41.13 mW power is consumed from a 1-V power supply during the 32-Gb/s PAM4 transmission.INDEX TERMS Driver circuits, equalization, feed-forward equalizer (FFE), non-return-to-zero (NRZ), pulse amplitude modulation (PAM4), transmitters.

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A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI

Cited by 39 publications

References 25 publications

Compact and Broadband ESD Protection I/O Pad Using Pad-Stacked Inductor

Compact and Broadband ESD Protection I/O Pad Using Pad-Stacked Inductor

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver

A 16/32 Gb/s Dual-Mode NRZ/PAM4 Voltage-Mode Transmitter With 2-Tap FFE

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