A high speed transmitter circuit for the ATLAS/CMS HL-LHC pixel readout chip

Abstract

In order to satisfy the high output bandwidth requirement imposed by the High Luminosity LHC, a high speed transmitter circuit was designed and integrated into the RD53A demonstrator chip for the phase 2 ATLAS/CMS pixel detector upgrade. A clock and data recovery circuit recovers clock from the 160 Mb/s data stream received by the chip, and provides the high speed clock to the serializer, where the 1.28 Gb/s output stream is formed from the 20-bit data words provided by the data encoding logic. The output stage employs a three-tap current-mode logic cable driver with adjustable tap weights for optimal pre-emphasis in order to compensate for the high frequency loss of the foreseen low mass cable. Each RD53A chip includes four output data lines, offering in total 5.12 Gb/s output bandwidth. The RD53A chip has been fabricated in a 65 nm CMOS technology. The output jitter was measured to be ∼ 20 ps (1 σ ) with pseudo random data at the nominal speed of 1.28 Gb/s.

Comparative evaluation of analogue front-end designs for the CMS Inner Tracker at the High Luminosity LHC

“…It is a mixed signal chip, having both analogue and digital circuits. It features custom-designed intellectual property blocks, such as clock data recovery and phase locked loop blocks [15] for the clock recovery from the command stream running at 160 Mb/s; a high speed output transmitter with a current mode logic cable driver [16] sending data at 1.28 Gb/s on up to four output lanes; and a shunt low-dropout regulator [17] for serial powering of the pixel modules. The chip size is 20.0 × 11.8 mm 2 , which is about half the size of the final chip, as it shares the chip reticle with CMS Outer Tracker chips.…”

A Clock and Data Recovery Circuit for the ALTAS/CMS HL-LHC Pixel Front End Chip in 65 nm CMOS Technology

“…Low voltage differential signaling (LVDS) is used for the command input and the recovered command and clock output signals. Gigabit CML drivers [2] are used for the serialized output and the VCO clock. The serializer input data can be provided by an included pseudo random binary sequence (PRBS) generator.…”

“…Therefore, reliable locking is essential for the full chip operation and correct start-up must be guaranteed. The high speed 1.28 GHz VCO clock is used by the serializer that feeds the output data to four 1.28 Gb/s lanes driven by a current mode logic (CML) stage with pre-emphasis [2]. To ensure high quality data transmission that is compatible with the low-power GBT (lpGBT) [3] communications IC, the CDR is required to achieve low jitter performance.…”