A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders

Lee, Seungbeom; Lee, Hanho

doi:10.1093/ietfec/e91-a.3.830

Cited by 37 publications

(42 citation statements)

References 6 publications

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“…The pipelined degree-computationless modified Euclidean (pDCME) algorithm and architecture [5] is used to obtain the error locator polynomial σ(x) and the error value polynomial ω(x) by solving the key equation…”

Section: Key Equation Solver Blockmentioning

confidence: 99%

“…The detailed explanation of pDCME algorithm and architecture was addressed in our previous paper [5].…”

Section: Key Equation Solver Blockmentioning

confidence: 99%

“…2 shows a proposed architecture and a timing chart for two-parallel 4-channel RS FEC architecture. The KES block [5] accepts the syndromes every 18 clock cycles, whereas two-parallel syndrome computation block accepts the received codeword every 127 or 128 clock cycles. Therefore, syndrome generation and application of correction have to be instantiated independent for each of the four decoding channels, while the KES block can be shared between all channels.…”

Section: Two-parallel Chien Search and Forney Algorithm Blockmentioning

confidence: 99%

“…and wireless systems, as well as in networking communications [1,2,3,4,5]. Due to increasing demand for high capacity of optical communications, the high-speed low-power implementations of RS decoders are desirable to meet higher data rate for system-level integration.…”

mentioning

confidence: 99%

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Two-parallel Reed-Solomon based FEC architecture for optical communications

Lee

Choi

Lee

2008

IEICE Electron. Express

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This paper presents a high-speed Forward Error Correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 10 and 40-Gb/s optical communication systems. A highspeed two-parallel RS(255, 239) decoder has been proposed and the derived structure can also be applied to implement the 10 and 40-Gb/s RS FEC architectures. The implementation results show that 16-Ch. RS FEC architecture can operate at a clock frequency of 160 MHz and has a throughput of 41 Gb/s for the Xilinx Virtex4 FPGA. Also, RS FEC operates at a clock frequency of 400 MHz and has a throughput of 102 Gb/s for 0.18-μm CMOS technology.

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Section: Key Equation Solver Blockmentioning

confidence: 99%

“…The detailed explanation of pDCME algorithm and architecture was addressed in our previous paper [5].…”

Section: Key Equation Solver Blockmentioning

confidence: 99%

Section: Two-parallel Chien Search and Forney Algorithm Blockmentioning

confidence: 99%

mentioning

confidence: 99%

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Two-parallel Reed-Solomon based FEC architecture for optical communications

Lee

Choi

Lee

2008

IEICE Electron. Express

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“…The architecture based on the conventional ME algorithm [5] is regular, but the hardware cost is high due to the required degree computation and comparison circuit. Highspeed ME architectures using pipelined multipliers to reduce the critical path delay were presented in [8] and [9]. However, the architectures are not area-efficient and require a larger number of clock cycles to solve the key equation.…”

Section: Introductionmentioning

confidence: 99%

High-Speed Low-Complexity Architecture for Reed-Solomon Decoders

Shieh

2010

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for ReedSolomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255,239) decoder design, implemented using the TSMC 0.18 μm process, can reach a throughput rate of 3 Gbps at an operating frequency of 375 MHz and with a total gate count of 27,271.

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