A High-Speed Optical Multi-Drop Bus for Computer Interconnections

Tan, Michael; Rosenberg, Paul; Yeo, Jong‐Souk; McLaren, Moray; Mathai, S.; Morris, Terry; Straznicky, Joseph; Jouppi, Norman P.; Kuo, Huei Pei; Wang, Shih-Yuan; Lerner, Scott; Kornilovich, Pavel; Meyer, N.; Bicknell, R. N.; Otis, C. E.; Seals, Lenward

doi:10.1109/hoti.2008.15

Cited by 15 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Tan et al [26] demonstrated a 10 Gbit/s optical link with GaAs based technology to implement an optical multi-drop memory bus. Vantrease et al [29] proposed Corona, which used photonic links to provide high bandwidth to the DRAM.…”

Section: Related Workmentioning

confidence: 99%

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

Therdsteerasukdi

Byun

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

View full text Add to dashboard Cite

Abstract-The demand for capacity and off-chip bandwidth to dynamic random-access memory (DRAM) will continue to grow as we integrate more cores onto a die. However, as the data rate of DRAM has increased, the number of dual in-line memory modules (DIMMs) supported on a multi-drop bus has decreased. Therefore, traditional memory systems are not sufficient to meet both these demands. We propose the DIMM tree architecture for better scalability by connecting the DIMMs as a tree. The DIMM tree architecture is able to grow the number of DIMMs exponentially with each level of latency in the tree. We also propose application of multiband radio-frequency interconnect (MRF-I) to the DIMM tree architecture for even greater scalability and higher throughput. The DIMM tree architecture without MRF-I was able to scale up to 64 DIMMs with only an 8% degradation in throughput over an ideal system. The DIMM tree architecture with MRF-I was able to increase throughput by 68% (up to 200%) on a 64-DIMM system over a 4-DIMM system. Finally, we propose the partitioned DIMM tree, which allows the scaling of a main memory system to a many-DIMM memory system while still maintaining high throughput. The partitioned DIMM tree is able to improve throughput by an average of 19% up to 35% over the DIMM tree with 256 DIMMs on a single channel.Index Terms-Integrated circuit interconnections, memory architecture, radio-frequency integrated circuits, random access memory.

show abstract

Section: Related Workmentioning

confidence: 99%

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

Therdsteerasukdi

Byun

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…Tan et al [6] demonstrated the feasibility of using an optical data bus for computer interconnections to avoid signal integrity issues inherent in using multi-drop electrical buses. Batten et al [7] described a custom opto-electrical crossbar network that connects DRAM modules to processors.…”

Section: Related Workmentioning

confidence: 99%

Performance Evaluation of a Multicore System with Optically Connected Memory Modules

Mejia

Amirtharajah

Farrens

et al. 2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

View full text Add to dashboard Cite

Abstract-Over the past years, there have been impressive advances in bandwidth, latency, and scalability of on-chip networks. However, unless the off-chip network bandwidth and latency are also improved, we might have unbalanced systems which will limit the improvements to overall system performance. In this paper, we show how dense wavelengthdivision multiplexing (DWDM) -based optical interconnects could be used to emulate multiple buses in a fully-buffered DIMM (FB-DIMM) -like memory system to improve both bandwidth and latency. We evaluate an optically connected memory using full-system simulations of an 8-core system running memory-intensive multithreaded workloads. We show that for the FFT benchmark, optically connected memory can reduce the average memory request latency by 29% compared to a single-channel DDR3 SDRAM system and provide an overall performance speedup of 1.20. We also show that at least two DDR3 memory channels are needed to match the performance of a single optical bus, which demonstrates the advantage of optical interconnects in terms of savings in the number of pins required.

show abstract

On-Chip Optical Ring Bus Communication Architecture for Heterogeneous MPSoC

Pasricha

Dutt

2012

Integrated Optical Interconnect Architectures for Embedded Systems

View full text Add to dashboard Cite

A High-Speed Optical Multi-Drop Bus for Computer Interconnections

Cited by 15 publications

References 11 publications

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

Performance Evaluation of a Multicore System with Optically Connected Memory Modules

On-Chip Optical Ring Bus Communication Architecture for Heterogeneous MPSoC

Contact Info

Product

Resources

About