A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems

Kim, Gil-Su; Ikeuchi, Katsuyoshi; Daito, Mutsuo; Takamiya, Makoto; Sakurai, Takayasu

doi:10.1109/3dic.2010.5751456

Cited by 8 publications

(4 citation statements)

References 6 publications

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“…To the authors' knowledge, the proposed work and [9] are the only ones that aim to add the feature of non-contact communication to a standard digital pad already available for automatic IC design flow based on synthesis, place & route of standard cells. All other solutions aim to achieve a high data rate for wireless wafer-level testing at the cost of integrating dedicated and area-consuming transceivers being based on either capacitive [1], [7], [8], [10] or inductive [11], [12] coupling. The wireless receiver is integrated under the top aluminum layer of the bonding pad, leaving the pad area unchanged so that the contactless mode of operation is obtained with no area overhead.…”

Section: Discussionmentioning

confidence: 99%

A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test

Scarselli

Perilli

Perugini

et al. 2015

IEEE Trans. Circuits Syst. I

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A receiver for capacitive coupled communication is embedded in a digital input/output pad to add the capacity for non-contact data communication, while maintaining size, ESD protection, and buffering functions unchanged, even in contact mode. The added feature allows non-contact probing of die pads and provides a reliable alternative solution to mechanical probing for electrical wafer sort testing of Systems-on-Chip (SoC) and Systems-in-Package (SiPs) because of elimination of pad damage and reduction of the force required to create stable electrical contacts between probe needles and pads. The proposed receiver detects the displacement current flowing through the capacitive channel created between the connecting probe needle and top metal pad surface when a transition in the input digital stimulus signal occurs. The receiver is designed to work up to 100 Mbit/s data rate with a power of 340 in a 40 nm CMOS process. The circuit trade-offs between frequency, amplitude of the step input and distance are discussed. Experimental results show that for a 5 V input voltage amplitude, the receiver allows correct data transmission at a distance up to 5 , which increases to 10 if the top aluminum layer is divided in two, using a customized I/O pad design. The feasibility of this non-contact testing approach was verified through electrical tests on two IP blocks, an LFSR, and a PLL with a scan chain, using a standard prober and a cantilever probe card designed with 19 needles of different lengths to enable both physical contact connections for power supply and non-contact capacitive coupling data communication for signals.

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Section: Discussionmentioning

confidence: 99%

A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test

Scarselli

Perilli

Perugini

et al. 2015

IEEE Trans. Circuits Syst. I

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“…The practical circuit design and implementation of wireless wafer-level testing via capacitive coupling are demonstrated in [4] [5]. Both show that capacitive coupling can achieve gigahertz communication rates with a short communication range.…”

Section: Coupling Techniques For Wireless Testingmentioning

confidence: 99%

“…An ideal common ground is assumed for the on-chip voltage transfer function in both (3) and (5). However, in reality both chips have different grounds, and these different grounds may affect channel gain significantly.…”

Section: On-chip Circuit Model Of Capacitive Couplingmentioning

confidence: 99%

See 1 more Smart Citation

Wireless wafer-level testing of integrated circuits via capacitively-coupled channels

Lee

Wentzloff

Hayes

2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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Wafer testing via direct-contact probe cards has long been an effective and relatively low-cost method for testing integrated circuit (IC) chips prior to packaging. However, the physical contact occurring between the wafer and automatic test equipment (ATE) has significant costs due to contact point deformation and the need for abrasive cleaning. In this paper, we investigate a non-contact testing technique that wirelessly couples an IC wafer and ATE, and serves as an alternative to conventional probe-card testing. We derive several analytical models for a capacitive testing channel. Electromagnetic field simulations results are presented that support the proposed channel models. We conclude that capacitance-based wireless testing is feasible for testing ICs in the 1-GHz range.

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Yield enhancement for 3D-stacked ICs: Recent advances and challenges

Jiāng

et al. 2012

17th Asia and South Pacific Design Automation Conference

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A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems

Cited by 8 publications

References 6 publications

A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test

A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test

Wireless wafer-level testing of integrated circuits via capacitively-coupled channels

Yield enhancement for 3D-stacked ICs: Recent advances and challenges

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