Wireless wafer-level testing of integrated circuits via capacitively-coupled channels

Abstract

Wafer testing via direct-contact probe cards has long been an effective and relatively low-cost method for testing integrated circuit (IC) chips prior to packaging. However, the physical contact occurring between the wafer and automatic test equipment (ATE) has significant costs due to contact point deformation and the need for abrasive cleaning. In this paper, we investigate a non-contact testing technique that wirelessly couples an IC wafer and ATE, and serves as an alternative to conventional probe-card testing. We derive several analytical models for a capacitive testing channel. Electromagnetic field simulations results are presented that support the proposed channel models. We conclude that capacitance-based wireless testing is feasible for testing ICs in the 1-GHz range.

A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test

“…As a first estimate, the capacitive coupling can be computed as , where is the coupling area and the air permittivity. For a more accurate analysis, the wireless interface was modeled by the S-matrix extracted from EM simulation, as in [9], of the 3D structure composed of two probe needles, taking into account crosstalk effects [21], [22]. Fig.…”

“…The circuit is designed to amplify injected currents at RX so any parasitic capacitive coupling on it (i.e., crosstalk) must be taken into consideration. The main contributors are crosstalk between adjacent channels [21], [22], mainly through capacitance and in Fig. 1, and spikes on power supplies connected to the pad ring which are coupled to RX by means of metal and device capacitances.…”