A high-performance very low-voltage current sense amplifier for nonvolatile memories

Conte, A.; Giudice, G. Lo; Palumbo, G.; Signorello, A.

doi:10.1109/jssc.2004.840985

Cited by 43 publications

(14 citation statements)

References 18 publications

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“…For a 64 KB of memory we have 512 cells connected to each bit-line, resulting in an equivalent capacitive load of about 450 fF [21]. A typical value equal to 1pF for bit-line capacitance and value for a load capacitance of 370 fF are used.…”

Section: Resultsmentioning

confidence: 99%

Low Power Double Gate Fin FET Based Sense Amplifier

Priyadarshni¹,

Singh²

2015

International Journal of Advanced Research in Computer and Comm

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Abstract:In this paper, a low power independent-gate, process variation tolerant double gate (DG) Fin FET based sense amplifier design has been proposed. As like RHIGSA, new design exploits the DICE (dual interlock cell) latch and the back gate of a double-gate Fin FET (DG Fin FET) device for dynamic compensation against process variation. But, there is change in tail transistor gate connections.,Which is dynamically controlled by intermediate signal in circuit. This design improves the power dissipation and show excellent tolerance to process parameter variations like temperature, V dd , thickness of oxide compared to Radiation hardend IGSA (RHIGSA) circuit and independent gate sense amplifier (IGSA). Proposed technique consumes 29.108% less power compare to RHIGSA.

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Section: Resultsmentioning

confidence: 99%

Low Power Double Gate Fin FET Based Sense Amplifier

Priyadarshni¹,

Singh²

2015

International Journal of Advanced Research in Computer and Comm

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show abstract

“…For a 64 kB of memory we have 512 cells connected to each bit-line, resulting in an equivalent capacitive load of about 450 fF [18]. A typical value equal to 1pF for bit-line capacitance and value for a load capacitance of 370 fF are used.…”

Section: Resultsmentioning

confidence: 99%

A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier

Rathod

Saxena

Dasgupta

2011

Microelectronics Reliability

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“…Hence (W/L) of each n-channel transistors has been chosen three times (W/L) of p-channel transistor. For a 64 kB of memory we have 512 cells connected to each bit-line, resulting in an equivalent capacitive load of about 450 fF [13]. A typical value equal to 1 pF for bit-line capacitance and value for a load capacitance of 370 fF are used in the simulation.…”

Section: High Bias Enable and Address Swing)mentioning

confidence: 99%

Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients

Rathod

Saxena

Dasgupta

2012

IET Circuits Devices Syst.

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In this study, the authors evaluate different schemes of address decoders based on bulk, single gate (SG) silicon-oninsulator (SOI) and double gate (DG) FinFET technology. Schemes differ in terms of back gate connections, and swing on the enable and address lines. The analysis for delay, power dissipation and critical charge has been carried out. Radiation induced single event transients and multiple bit upsets in address decoder have been studied. For radiation hardened applications, tied gate configuration has been found to be good choice over bulk, SG-SOI and independent gate configurations. The effect of process parameter variations on different schemes has been studied. HSPICE simulations have been performed with 45 nm bulk, SG-SOI and DG-FinFET predictive technology models.

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A high-performance very low-voltage current sense amplifier for nonvolatile memories

Cited by 43 publications

References 18 publications

Low Power Double Gate Fin FET Based Sense Amplifier

Low Power Double Gate Fin FET Based Sense Amplifier

A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier

Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients

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