A High Performance Single Chip LSI for Error Correction of Optical Disk Memory

Abstract

A Single chip error correcting LSI of Reed-Solomon long minimum distance code (d=<17) has been developed for optical disk memory. High speed decoding of error correcting code has been realized by internal multi-processing architecture, in which interleaving, syndrome calculation, error correction, and data inter facing with the host computer are processed simultaneously. In addition to the adoption of a multiprocessor configuration, high speed hardware for error correction and detection is employed to realize “on the fly” decoding which decodes any decodable errors of a code of length n=20 distance d=<17 within 600 clocks. Euclidian algorithm is applied for correction of errors, and unknown error locations, besides, a newly developed recursive algorithm is applied to erasure correction if error locations are identified beforehand. This contributes to both high speed decoding and hardware reduction. Check words and other parameters are selectable and these are set up in registers via an external micro-controller bus. A Small Computer System Interface(SCSI-2) has been provided as the system interface.