A high-performance microarchitecture with hardware-programmable functional units

Abstract

This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive datapath operations. In this paper, we concentrate on the microarchitectural design of the simplest form of PRISC-a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language compilation techniques that are needed to successfully build PRISC and, we present performance results from a proof-of-concept study. With the inclusion of a single 32-bit-wide PFU whose hardware cost is less than that of a 1 kilobyte SRAM, our study shows a 22% improvement in processor performance on the SPECint92 benchmarks.

Reconfigurable Computing Architectures

“…As chip capacities grew, research explored architectures that integrated an FPGA or reconfigurable array on the same die with the processor [8]- [10]. Key concerns included the visible architectural model for the array, how state was shared with the configurable array, how different timing requirements of the processor and array should be accommodated, and how to maximize the bandwidth and minimize the latency required to communicate with the array.…”

“…Key concerns included the visible architectural model for the array, how state was shared with the configurable array, how different timing requirements of the processor and array should be accommodated, and how to maximize the bandwidth and minimize the latency required to communicate with the array. The reconfigurable logic could be integrated as a programmable functional unit for a RISC processor [8], [11], share state with the conventional register file, and manage the reconfigurable array as a cache of programmable instructions [12].…”

Fundamental Underpinnings of Reconfigurable Computing Architectures

“…Such a profile might benefit from an architecture that had two componentsVone that focused on area minimization for the 90% of the code that runs only 10% of the time, and another focused on maximizing computational density and minimizing the energy for the 10% of the code that runs 90% of the time. This has led to designs that combine the area efficiency of a processor with the computational density and energy efficiency of a spatially reconfigurable compute engine, starting from Estrin's Fixed+Variable computer [40], through a host of design proposals (e.g., [41], [42]), leading to today's FPGAs with embedded processors, such as Xilinx's Zynq and Altera's Arria and Cyclone V SoC.…”

An Architecture for Reconfigurable Multi-core Explorations

“…There has been a lot of reconfigurable processor research in the past, most notably: PRISC [1] is a RISC based microprocessor that includes reprogrammable function units, OneChip [2] is based on MIPS and integrates a tightly coupled reconfigurable core. Chimaera [3] integrates a superscalar processor with a reconfigurable function unit; the Chimaera C compiler has the ability to automatically map instructions to the reconfigurable unit.…”