An Architecture for Reconfigurable Multi-core Explorations

Serres, Olivier; Narayana, Vikram K.; El‐Ghazawi, Tarek

doi:10.1109/reconfig.2011.10

Cited by 7 publications

(4 citation statements)

References 12 publications

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“…A complete multicore reconfigurable platform can provide a rich and flexible environment for application programmers [40]. Each processor core has a coupled reconfigurable coprocessor unit in that architecture, which allows the extension of a processor's instruction set to run applications.…”

Section: Related Workmentioning

confidence: 99%

Hardware Update through Digital TV Signals

et al. 2021

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This paper presents a new hardware reconfiguration approach named hardware reconfiguration through digital television (HARD), which can update FPGA hardware modules based on digital TV (DTV) signals. Such a scheme allows several synthesized hardware cores (bitstreams) signaled and broadcast through open DTV signals via data streaming to be identified, acquired, decoded, and then used for system updates. Reconfiguration data are partitioned, encapsulated into private sections, and then sent in a carrousel fashion in order to be recovered by modified receivers. Service information content, specially designed for identifying and describing the characteristics of multiplexed hardware bitstreams, was added to the transmitted signal and provided all necessary information in the traditional DTV style. The receiver framework, in turn, checked whether those characteristics corresponded to its embedded reconfigurable devices and, if a match was found, it reassembled the related bitstreams and reconfigured the respective internal circuits. Experiments performed with an implementation of the proposed methodology confirmed its feasibility and showed that remounting and reconfiguration times were satisfactory and presented no blocking aspect. Finally, HARD can be used in several designs regarding intelligent reconfigurable devices, minimize device costs in the long term, and provide better hardware reuse.

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Section: Related Workmentioning

confidence: 99%

Hardware Update through Digital TV Signals

et al. 2021

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“…They focus on two reference architectures: one with shared memory used only for task migration, that requests a complex programming model, and another one with shared memory connected through a multiport memory controller that allows reading and writing memory locations simultaneously. Serres et al [15] presented a reconfigurable multicore scenario based on LEON3 soft-processor and proposed a co-processor interface for each core.…”

Section: Multicore Platforms Based On Soft-coresmentioning

confidence: 99%

A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system

et al. 2016

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In recent years, the use of multiprocessor systems has become increasingly common. Even in the embedded domain, the development of platforms based on multiprocessor systems or the porting of legacy single-core applications are frequent needs. However, such designs are often complicated, as embedded systems are characterized by numerous non-functional requirements and a tight hardware/software integration. This work proposes a methodology for the development and validation of an embedded multiprocessor system. Specifically, the proposed method assumes the use of a portable, open source API to support the parallelization and the possibility of prototyping the system on a field-programmable gate array. On this basis, the proposed flow allows an early exploration of the hardware configuration space, a preliminary estimate of performance, and the rapid development of a system able to satisfy the design specifications. An accurate assessment of the actual performance of the system is then enforced by the use of an hardware-based profiling subsystem. The proposed design flow is described, and a version specifically designed for LEON3 processor is presented and validated. The application of the proposed methodology in a real case of industrial study is then presented and analyzed.

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“…A softcore Leon3 processor was extended with our proposed PGAS hardware support for shared addressing by using the reserved SPARC V8 coprocessor instructions. Extending the Leon3 softcore processor via the coprocessor interface is described in Serres et al [2011b]. The Leon3 softcore processor implements the 32-bit SPARC V8 architecture with a seven-stage pipeline.…”

Section: Fpga Prototyping With Leon3mentioning

confidence: 99%

Enabling PGAS Productivity with Hardware Support for Shared Address Mapping

Serres

Kayi

Anbar

et al. 2015

ACM Trans. Archit. Code Optim.

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Due to its rich memory model, the partitioned global address space (PGAS) parallel programming model strikes a balance between locality-awareness and the ease of use of the global address space model. Although locality-awareness can lead to high performance, supporting the PGAS memory model is associated with penalties that can hinder PGAS's potential for scalability and speed of execution. This is because mapping the PGAS memory model to the underlying system requires a mapping process that is done in software, thereby introducing substantial overhead for shared accesses even when they are local. Compiler optimizations have not been sufficient to offset this overhead. On the other hand, manual code optimizations can help, but this eliminates the productivity edge of PGAS. This article proposes a processor microarchitecture extension that can perform such address mapping in hardware with nearly no performance overhead. These extensions are then availed to compilers through extensions to the processor instructions. Thus, the need for manual optimizations is eliminated and the productivity of PGAS languages is unleashed. Using Unified Parallel C (UPC), a PGAS language, we present a case study of a prototype compiler and architecture support. Two different implementations of the system were realized. The first uses a full-system simulator, gem5, which evaluates the overall performance gain of the new hardware support. The second uses an FPGA Leon3 soft-core processor to verify implementation feasibility and to parameterize the cost of the new hardware. The new instructions show promising results on all tested codes, including the NAS Parallel Benchmark kernels in UPC. Performance improvements of up to 5.5× for unmodified codes, sometimes surpassing handoptimized performance, were demonstrated. We also show that our four-core FPGA prototype requires less than 2.4% of the overall chip's area.

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An Architecture for Reconfigurable Multi-core Explorations

Cited by 7 publications

References 12 publications

Hardware Update through Digital TV Signals

Hardware Update through Digital TV Signals

A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system

Enabling PGAS Productivity with Hardware Support for Shared Address Mapping

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