A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

Joshi, Rajiv V.; Kim, Keunwoo; Williams, R.; Nowak, E.; Chuang, Ching-Te

doi:10.1109/vlsid.2007.182

Cited by 25 publications

(11 citation statements)

References 3 publications

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“…Several data storage components are modeled by the CACTI-PVT cache model in FinCANON, including the L1 instruction and data caches, L2 caches, RFs, translation lookaside buffers, reservation stations, and so on. FinCANON supports five types of FinFET memory cells that can be used in these data storage components: 1) 4T [44]; 2) pass-gate feedback (PGFB) 6T [45]; 3) row-based back-gate biasing (RBGB) 6T [46]; 4) ASG 6T [47]; and 5) 8T [48]. PGFB cells are fast but consume high leakage power.…”

Section: Cache and Noc Models In Mcpat-pvtmentioning

confidence: 99%

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

Tang

Yang

Lee

et al. 2015

IEEE Trans. VLSI Syst.

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As technology has moved into the deepsubmicrometer regime, the shrinking feature size has placed a considerable stress on CMOS fabrication due to short-channel effects (SCEs) and excessive leakage. Although many research efforts have been devoted to seeking system-level solutions, underlying transistor-level solutions are still urgently required to overcome these obstacles. FinFETs have emerged as promising substitutes for conventional CMOS due to their superior control of SCEs and process scalability. However, FinFETs still face lithographic and workfunction engineering challenges, in addition to those posed by supply voltage and temperature variations across the integrated circuit (IC). These lead to process, supply voltage, and temperature (PVT) variations in FinFET ICs, which, in turn, lead to large spreads in delay and leakage. In this paper, we present a multicore power, area, and timing (McPAT)-PVT, an integrated framework for the simulation of power, delay, as well as PVT variations of FinFET-based processors. McPAT-PVT uses a FinFET design library, consisting of logic and memory cells, to model circuit-level characteristics as well as their PVT variation trends. It is based on macromodels, derived from very accurate TCAD device simulations that characterize various functional units in a processor under PVT variations, making yield analysis for timing and power for processor components possible. McPAT-PVT can model both shorted-gate (SG) and asymmetric-workfunction shorted-gate (ASG) FinFET-based processors. Combining these macromodels with a FinFET-based CACTI-PVT cache model and an ORION-PVT on-chip network model, McPAT-PVT is able to simulate a delay and power consumption of all processor components under PVT variations.We present extensive simulation results to demonstrate its efficacy, including for an alpha-like processor and multicore simulations based on Princeton Application Repository for Shared-Memory Computers benchmarks. Results show that the ASG FinFET-based processor implementation has 73× lower leakage power and 2.6× lower total power relative to the SG FinFET-based processor implementation for the same performance, with <1% area penalty.

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Section: Cache and Noc Models In Mcpat-pvtmentioning

confidence: 99%

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

Tang

Yang

Lee

et al. 2015

IEEE Trans. VLSI Syst.

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“…Fabrication issues, detailed discussions on 4T/6T FinFET SRAM circuit design, and brief explanations on the effect of process variations are available in Balasubramanian [2006], Guo et al [2005], Joshi et al [2007], Ananthan et al [2004], Xiong and Bokor [2003], Cakici et al [2007], and Joshi et al [2004]. 2T/3T1D DRAM design in bulk CMOS/SOI technology has been explored in Luk and Dennard [2005b], Luk and Dennard [2005a], Luk et al [2006], and Chang et al [2007].…”

Section: Related Workmentioning

confidence: 99%

“…Increased scaling at each successive technology node has placed considerable stress on SRAM technology due to the effects of process variations on performance, stability and standby leakage power consumption. In order to circumvent the SRAM scaling/variability problem, researchers have considered replacing bulk SRAM with 2T/3T1D bulk DRAM [Liang et al 2007;Luk and Dennard 2005b], or switching to a multi-gate implementation such as FinFET SRAM [Guo et al 2005;Joshi et al 2007;Ananthan et al 2004]. 3T1D DRAM was shown to meet the performance requirements of an L1 cache memory in the temporal window of repeated accesses/writes, thereby obviating the need for a static memory, in Liang et al [2007].…”

Section: Introductionmentioning

confidence: 99%

Gated-diode FinFET DRAMs

Bhoj

Jha

2010

J. Emerg. Technol. Comput. Syst.

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Scaling bulk CMOS SRAM technology for on-chip caches beyond the 22nm node is questionable, on account of high leakage power consumption, performance degradation, and instability due to process variations. Recently, two-three transistor one gated-diode (2T/3T1D) DRAMs were proposed as alternatives to address the SRAM variability problem, with an emphasis on highactivity embedded cache applications. They are highly competitive to SRAM in terms of performance, while having a smaller power and area footprint at lower technology nodes. The current evolutionary trend in transistor structures is moving toward an era of multigate devices, which makes it necessary to identify design issues and advantages of gated-diode DRAMs implemented in a multigate technology.In this work, we address gated-diode DRAM design in FinFET technology using mixed-mode 2D-device simulations. We revisit the model of internal voltage gain in bulk gated diodes and extend it to provide quantitative insight into designing Fin gated diodes, that is, gated diodes in FinFET technology. To this effect, we propose FinFET variants of the bulk gated-diode configuration and identify parameters that are critical to enhancing the retention time and read current in 2T/3T1D FinFET DRAMs. Additionally, we show the superiority of 2T1D FinFET DRAM over 6T FinFET SRAM having pass-gate feedback (6T PGFB) and 2T1D bulk DRAM under the effect of physical parameter process variations using a quasi-Monte Carlo method implemented in FinE, an environment we have developed for double-gate circuit design that integrates Sentaurus TCAD from Synopsys with the Spice3-UFDG double-gate compact model from University of Florida, under a single framework. Finally, we present a new tunable threshold gated diode FinFET amplifier which uses an n-type gated diode for voltage-boosting, along with a p-type gated diode for zerosuppression.

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“…Moreover, various scaling obstacles are faced by bulk CMOS, such as short-channel effects (SCEs), process variations, dopant fluctuations, etc. Although circuit-level techniques like adaptive body-biasing (ABB) [17] has been proposed to reduce leakage, it has been reported in [12] that the role of well/body bias in threshold voltage modulation is becoming less effective as CMOS scales down. Therefore, underlying transistor-level solutions are needed to overcome the above problems.…”

Section: Introductionmentioning

confidence: 99%

FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing

Lee

Jha

2009

2009 IEEE International Conference on Computer Design

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On-chip interconnection networks are fast becoming significant power-consumers in high-performance chip multiprocessors (CMPs). Increased power consumption leads to more heat, adversely degrades system reliability, and may increase the cost of cooling IC packages. This situation becomes even worse as bulk CMOS scales further into the nanometer regime because of excessive leakage power due to short-channel effects. In this paper, we explore the use of FinFETs, which are promising substitutes for bulk CMOS at the 32nm node and beyond, to design on-chip network routers. We present a detailed design of a variable pipeline stage router (VPSR) targeted at FinFET technology. We employ a dynamic power management scheme, which we call adaptive back-gate biasing (ABGB), for FinFET implementations. We evaluate VPSR and ABGB on a simulation platform specifically designed for power and performance simulations for FinFET-based interconnection networks. The results show that VPSR is able to successfully adapt its power consumption to incoming traffic, with a resultant 20% reduction in power at almost no impact on latency.

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A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

Cited by 25 publications

References 3 publications

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

Gated-diode FinFET DRAMs

FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing

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