A high performance hardware architecture for the H.264/AVC half-pixel interpolation unit

Corrêa, Marcel; Schoenknecht, Mateus Thurow; Dornelles, Robson; Agostini, Luciano

doi:10.1109/spl.2010.5482998

Cited by 7 publications

(6 citation statements)

References 3 publications

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“…As future works, we plan to integrate the eighth-pixel chrominance interpolation architecture with other ME and MC modules that are being designed in parallel works [5,6].…”

Section: Discussionmentioning

confidence: 99%

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H.264/AVC Eighth Pixel MC Chrominance interpolation hardware targeting very high resolution videos

Schoenknecht

Timm

Rosa

et al. 2011

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS)

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This paper presents a hardware design for the H.264/AVC Eighth-Pixel Chrominance Interpolation Unit that is a part of the Motion Compensation Unit. The architecture was optimized to reach a high throughput through a balanced pipeline and internal parallelism exploration. The design was described in VHDL and synthesized to a Xilinx Virtex2p FPGA. The best performance results achieve an operation frequency of 100 MHz, processing up to 42 QHDTV frames (3840x2048 pixels) per second.

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“…As future works, we plan to integrate the eighth-pixel chrominance interpolation architecture with other ME and MC modules that are being designed in parallel works [5,6].…”

Section: Discussionmentioning

confidence: 99%

“…Based in the presented results and in previous works of our group [5,6] we decided to consider a ME that support only 8x8 blocks.…”

Section: Experimental Evaluationmentioning

confidence: 99%

H.264/AVC Eighth Pixel MC Chrominance interpolation hardware targeting very high resolution videos

Schoenknecht

Timm

Rosa

et al. 2011

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS)

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“…Interpolation Unit Architecture. Our design uses an optimized architecture for the half-pixel interpolation unit, which was initially presented in a previous work [8]. This architecture uses an efficient arrangement of interpolation samples, and it needs only 34 clock cycles to generate an interpolated area around an 8 × 8 block.…”

Section: Half-pixelmentioning

confidence: 99%

“…One of the improvements of our Half-Pixel Interpolation Unit is the use of an optimized processing unit (PU) when compared with that presented in [8]. The new PU uses fewer adders, and it was validated to generate all half-pixel types.…”

Section: Processing Unitmentioning

confidence: 99%

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A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos

Corrêa

Schoenknecht

Dornelles

et al. 2011

International Journal of Reconfigurable Computing

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This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV () in real time (30 frames per second). It also presents an optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The interpolation process is interleaved with the SAD calculation and comparison, allowing the high throughput. The architecture was fully described in VHDL, synthesized for two different Xilinx FPGA devices, and it achieved very good results when compared to related works.

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Analysis and architecture design of scalable fractional motion estimation for H.264 encoding

Vasiljevic

2012

Integration

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A high performance hardware architecture for the H.264/AVC half-pixel interpolation unit

Cited by 7 publications

References 3 publications

H.264/AVC Eighth Pixel MC Chrominance interpolation hardware targeting very high resolution videos

H.264/AVC Eighth Pixel MC Chrominance interpolation hardware targeting very high resolution videos

A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos

Analysis and architecture design of scalable fractional motion estimation for H.264 encoding

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