A high performance floating-point special function unit using constrained piecewise quadratic approximation

De, Davide; Petra, Nicola; Strollo, A.G.M.

doi:10.1109/iscas.2008.4541457

Cited by 6 publications

(4 citation statements)

References 12 publications

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“…For example, the SIMT core in the NVIDIA GT240 has eight fully pipelined floating point units (FPUs), eight pipelined integer units (IUs) and two special function units (SFUs) to execute transcendental instructions such as sine, cosine, reciprocal, and square root. In our power model, we used the area numbers published by Sameh et al [20] for FPUs, the results of Caro et al [21] for power and area of the SFUs with scaling for the desired process technology, and our own measurements for power of integer units and floating point units (see Section III-D). 4) Load/Store Unit: The load-store unit (LDSTU) is functionally responsible for handling instructions that read or write any kind of memory.…”

Section: Modeled Architecturementioning

confidence: 99%

How a single chip causes massive power bills GPUSimPow: A GPGPU power simulator

Lucas¹,

Lal²,

Andersch³

et al. 2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Modern GPUs are true power houses in every meaning of the word: While they offer general-purpose (GPGPU) compute performance an order of magnitude higher than that of conventional CPUs, they have also been rapidly approaching the infamous "power wall", as a single chip sometimes consumes more than 300W. Thus, the design space of GPGPU microarchitecture has been extended by another dimension: power. While GPU researchers have previously relied on cycle-accurate simulators for estimating performance during design cycles, there are no simulation tools that include power as well. To mitigate this issue, we introduce the GPUSimPow power estimation framework for GPGPUs consisting of both analytical and empirical models for regular and irregular hardware components. To validate this framework, we build a custom measurement setup to obtain power numbers from real graphics cards. An evaluation on a set of well-known benchmarks reveals an average relative error of 11.7% between simulated and hardware power for GT240 and an average relative error of 10.8% for GTX580. The simulator has been made available to the public [1].

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Section: Modeled Architecturementioning

confidence: 99%

How a single chip causes massive power bills GPUSimPow: A GPGPU power simulator

Lucas¹,

Lal²,

Andersch³

et al. 2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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“…We followed the method proposed in [7] to generate the coefficients which can result in a smaller table than that of [6]. The function to compute 1/d is approximated as follows:…”

Section: Division By 1/d Polynomial Approximationmentioning

confidence: 99%

Power dissipation in division

Liu

Nannarelli

2008

2008 42nd Asilomar Conference on Signals, Systems and Computers

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Abstract-A few classes of algorithms to implement division in hardware have been used over the years: division by digit-recurrence, by reciprocal approximation by iterative methods and by polynomial approximation. Due to the differences in the algorithms, a comparison among their implementation in terms of performance and precision is sometimes hard to make. In this work, we use power dissipation and energy consumption as metrics to compare among those different classes of algorithms. There are no previous works in the literature presenting such a comparison.

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“…The precision of results and the performance are related with the size of look-up table storing the polynomial coefficients. The efforts of making the table smaller are continued since the size of look-up table occupies large portion of an SFU; up to 40% of the total area of an SFU according to the implementation methods [4].…”

Section: Introductionmentioning

confidence: 99%

Bank-partition and multi-fetch scheme for floating-point special function units in multi-core systems

Kim

Chung

Kim

et al. 2009

2009 IEEE International Symposium on Circuits and Systems

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A table loader unit with bank-partition and multifetch feature is proposed for multiple special function units in multi-core systems. By sharing the look-up tables among special function units, the proposed scheme reduces look-up table size by 54% and read power consumption by 75% for 8-core/4-bank configuration. However, the performance loss is less than 25% for various benchmark applications. As the number of cores increases for the future multi-core systems, the effects of area and power saving by the proposed schemes increase, but the performance loss is reduced.

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A high performance floating-point special function unit using constrained piecewise quadratic approximation

Cited by 6 publications

References 12 publications

How a single chip causes massive power bills GPUSimPow: A GPGPU power simulator

How a single chip causes massive power bills GPUSimPow: A GPGPU power simulator

Power dissipation in division

Bank-partition and multi-fetch scheme for floating-point special function units in multi-core systems

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