A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)

Zhang, Yu; Chen, Dongdong; Choi, Younhee; Chen, Li; Ko, Seok‐Bum

doi:10.1016/j.micpro.2010.04.006

Cited by 55 publications

(45 citation statements)

References 10 publications

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“…The architectures have been implemented (placed and routed) on Xilinx Virtex4, Virtex5 and Virtex7 FPGA families resulting in the fastest reported implementations to date to the best knowledge of the authors. On the Virtex4 our ECC point multiplication over GF (2 163 ) takes 5.32 µs with 13418 slices -is faster than the fastest previously reported Virtex 4 design [14] and also faster than the fastest reported design to date (5.48 µs) which was on a Virtex 5 [13]. On Virtex5, our design over GF (2 163 ) is not only even faster at 4.91 µs but also smaller than that of [13].…”

Section: Discussionmentioning

confidence: 66%

“…Our HPECC implementation on Virtex4 consumes 38% less area and shows 31% speed improvement. Again, our work uses less arithmetic (163 bit multiplier) resource to gain 2.33 times improvement in the area-time metric(Slices x Time x 10 -3 ) as compared to the work in [14]. In [16], the authors presented a high speed design that used 17929 slices to attain 9.60 µs for the point multiplication time; meanwhile, our proposed work on Virtex4 is 45% faster than that in [16] and consuming less area.…”

Section: Implementation Resultsmentioning

confidence: 94%

“…For Virtex4, the previous highest speed implementation is presented in [14] and consumed 20807 slices to achieve 7.72 µs using three 82 bit parallel multiplier cores. Our HPECC implementation on Virtex4 consumes 38% less area and shows 31% speed improvement.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…Many high performance ECC processor implementations on FPGA have been reported in the literature; the most relevant are presented in [10], [11], [12], [13], [14], [15], [16], [17], [20], [21], [22], and [23]. The common optimizing technique of high speed designs is the reduction of latency (number of clock Z. U.…”

Section: Introductionmentioning

confidence: 99%

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High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan

Benaïssa

2017

IEEE Trans. VLSI Syst.

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Abstract-In this paper, a novel high speed ECC processor implementation for point multiplication on Field Programmable Gate Array (FPGA) is proposed. A new segmented pipelined fullprecision multiplier is used to reduce the latency and the LopezDahab (LD) Montgomery point multiplication algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles required. The proposed ECC architecture has been implemented on Xilinx FPGAs Virtex4, Virtex5 and Virtex7 families. To our knowledge, our single multiplier and three multipliers based designs show the fastest performance to date when compared to reported works individually. Our one multiplier based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 µs at 210 MHz), on Virtex5 (4.91 µs at 228 MHz), and on the more advanced Virtex7, (3.18 µs at 352 MHz). Finally, the proposed three multiplier based ECC implementation is the first work reporting the lowest number of clock cycles and the fastest ECC processor design on FPGA (450 clock cycles to get 2.83 µs on Virtex7).

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Section: Discussionmentioning

confidence: 66%

Section: Implementation Resultsmentioning

confidence: 94%

Section: Implementation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan

Benaïssa

2017

IEEE Trans. VLSI Syst.

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“…In the double and add algorithm, the number of computations required in each iteration depends on the key bit and is easily prone to power analysis attacks. In the proposed hardware architecture the algorithm used for implementing the point multiplication unit is the Lopez -Dahab algorithm in [15]. The two major advantages of the Lopez-Dahab algorithm are (i) use of projective Figure 2.…”

Section: Ecpm Unitmentioning

confidence: 99%

Hardware Implementation of an Efficient Key Management Scheme for Wireless Sensor Networks

Jilna¹,

Deepthi²,

Jayaraj³

2016

IJICR

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Efficient hardware implementations of point multiplication for binary Edwards curves

Rashidi

2018

Circuit Theory & Apps

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SummaryThis paper presents efficient and fast hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on extremely fast complete differential addition and doubling formulas. These new complete differential addition formulas are performed for general and special cases of BECs with cost of 5M + 4S + 2D and 5M + 4S + 1D, respectively, where, M, S, and D denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of the BECs, proposed structures are implemented based on 3 and 1 pipelined digit‐serial Gaussian normal basis multipliers. In the design by 3 multipliers, computation of point addition and point doubling is performed concurrently. But in the second implementation for low‐cost design with low number of hardware resources, these computations are implemented by 1 multiplier. Also, in the special case of BECs, 2 structures are proposed for achieving the highest degree of parallelization and utilization of resources by using 3 and 2 field multipliers. Implementation results of the proposed architectures based on Virtex‐5 XC5VLX110, Virtex‐4 XC4VLX100, and Arria‐10 10AX115U4F45I3SG FPGAs for 2 fields and are achieved. The results show improvements in terms of execution time, area, and efficiency for the proposed structures compared with previous works.

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A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)

Cited by 55 publications

References 10 publications

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Hardware Implementation of an Efficient Key Management Scheme for Wireless Sensor Networks

Efficient hardware implementations of point multiplication for binary Edwards curves

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