High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Khan, Zia Uddin Ahamed; Benaïssa, Mohammed

doi:10.1109/tvlsi.2016.2574620

Cited by 78 publications

(108 citation statements)

References 28 publications

(83 reference statements)

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“…Several FPGA-based ECC architectures, either for high speed [4][5][6][7][8][9][10][11] or low resource applications [12][13][14][15], are available in the literature.…”

Section: Related Workmentioning

confidence: 99%

“…To reduce the number of CCs, various techniques have been employed in [4][5][6][7][8][9][10][11]. For example, the work in [4] presents three complex instructions while instruction level parallelism is used in [6,8] to reduce the number of required CCs.…”

Section: High-speed Applicationsmentioning

confidence: 99%

“…To implement PM operation, National Institute of Standards and Technology (NIST) have proposed a number of standard elliptic curves over the prime field GF(p) and binary extension field GF(2 m ) [3]. However, GF(2 m ) field is commonly used for efficient hardware implementations [4][5][6][7][8][9][10][11][12][13][14][15]. Furthermore, field-programmable-gate-array (FPGA) based designs of ECC are gaining more popularity due to the provision of its reconfigurability, availability (commonly available to everyone in the market) and shorter development time scales.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Throughput/area optimised pipelined architecture for elliptic curve crypto processor

Imran

Rashid

Jafri

et al. 2019

IET Computers & Digital Techniques

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A pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first; by pipelining the arithmetic unit to reduce the critical path delay. Second, by reducing the number of clock cycles (latency), which is achieved through careful scheduling of computations involved in point addition and point doubling. These two factors thus, help in reducing the time for one point multiplication computation. On the other hand, the small area overhead for this design gives a higher throughput/area ratio. Consequently, the proposed architecture is synthesised on different FPGAs to compare with the state-of-the-art. The synthesis results over GF(2 m) show that the proposed design can work up to a frequency of 369, 357 and 337 MHz when implemented for m = 163, 233 and 283 bit key lengths, respectively, on Virtex-7 FPGA. The corresponding throughput/slice figures are 42.22, 12.37 and 9.45, which outperform existing implementations.

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“…Several FPGA-based ECC architectures, either for high speed [4][5][6][7][8][9][10][11] or low resource applications [12][13][14][15], are available in the literature.…”

Section: Related Workmentioning

confidence: 99%

Section: High-speed Applicationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Throughput/area optimised pipelined architecture for elliptic curve crypto processor

Imran

Rashid

Jafri

et al. 2019

IET Computers & Digital Techniques

View full text Add to dashboard Cite

show abstract

“…The public key is used for encryption to provide data confidentiality during communication. ECC is implemented in smart card because of its smaller key size and less computational complexity relative to RSA cryptosystem [2]. This makes it attractive and suitable for such applications.…”

Section: Introductionmentioning

confidence: 99%

Improving the Performance of {0,1,3}-NAF Recoding Algorithm for Elliptic Curve Scalar Multiplication

AbdulRaheem¹,

Yasin²,

Udzir³

et al. 2019

IJACSA

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Although scalar multiplication is highly fundamental to elliptic curve cryptography (ECC), it is the most time-consuming operation. The performance of such scalar multiplication depends on the performance of its scalar recoding which can be measured in terms of the time and memory consumed, as well as its level of security. This paper focuses on the conversion of binary scalar key representation into {0, 1, 3}-NAF non-adjacent form. Thus, we propose an improved {0, 1, 3}-NAF lookup table and mathematical formula algorithm which improves the performance of {0, 1, 3}-NAF algorithm. This is achieved by reducing the number of rows from 15 rows to 6 rows, and reading two (instead of three) digits to produce one. Furthermore, the improved lookup table reduces the recoding time of the algorithm by over 60% with a significant reduction in memory consumption even with an increase in key size. Specifically, the improved lookup table reduces the memory consumption by as much as 75% for the big key, which shows its higher level of resilience to side channel attacks.

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“…The public key is used for encryption to provide data confidentiality during communication. ECC is implemented in smart card because of its smaller key size and less computational complexity relative to RSA cryptosystem [2] and [3]. This makes it attractive and suitable for such applications [4].…”

Section: Introductionmentioning

confidence: 99%

New Quintupling Point Arithmetic 5P Formulas for Lopez-Dahab Coordinate over Binary Elliptic Curve Cryptography

AbdulRaheem¹,

Yasin²,

Udzir³

et al. 2019

IJACSA

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In Elliptic Curve Cryptography (ECC), computational levels of scalar multiplication contains three levels: scalar arithmetic, point arithmetic and field arithmetic. To achieve an efficient ECC performance, precomputed points help to realize a faster computation, which takes away the need to repeat the addition process every time. This paper introduces new quintupling point (5P) formulas which can be precomputed once and can be reused at the scalar multiplication level. We considered mixed addition in Affine and Lŏpez-Dahab since the mixed addition computation cost is better than the traditional addition in Lŏpez-Dahab coordinates over binary curve. Two formulas are introduced for the point quintupling which and , the cost of the two formulas are and respectively. The two formulas are proven as valid points. The new quintupling point can be implemented with different scalar multiplication methods.

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High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

Cited by 78 publications

References 28 publications

Throughput/area optimised pipelined architecture for elliptic curve crypto processor

Throughput/area optimised pipelined architecture for elliptic curve crypto processor

Improving the Performance of {0,1,3}-NAF Recoding Algorithm for Elliptic Curve Scalar Multiplication

New Quintupling Point Arithmetic 5P Formulas for Lopez-Dahab Coordinate over Binary Elliptic Curve Cryptography

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