A high performance D-flip flop design with low power clocking system using MTCMOS technique

Dobriyal, Paanshul; Sharma, K. G.; Sethi, Manan; Sharma, Geetanjali

doi:10.1109/iadcc.2013.6514453

Cited by 9 publications

(7 citation statements)

References 6 publications

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“…During active mode the self adjustable circuit supplies maximum voltage to the load and in the silent mode lower voltage to the load. A clocked pair shared flip-flop (CPSFF) using Multi-Threshold CMOS technique is presented in [17]. Double edge triggering and low swing clocking is implemented in the clocking system.…”

Section: Literature Reviewmentioning

confidence: 99%

Leakage Reduction Technique and Analysis of CMOS D Flip Flop

Sridhara¹,

Biradar²

2016

VLSICS

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Power consumption and delay are the two major issues in the design of today's VLSI based battery operated portable electronic devices. Memory units in these devices are made of flip flops and each flip flop will consume more power in both active and idle conditions. Through this paper we try to explore alternate techniques to implement D flip-flop with the aim of reducing leakage power, delay and to increase the speed. All the different configurations of D flip-flops are simulated using HSPICE in 90nm process technology with BSIM4 MOS transistor models of level 54.

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Section: Literature Reviewmentioning

confidence: 99%

Leakage Reduction Technique and Analysis of CMOS D Flip Flop

Sridhara¹,

Biradar²

2016

VLSICS

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“…The CDMFF shown in the Figure 1(b) [8] incorporates conditional data mapping (CDM) technology. In the flip-flops when the inputs are (0, 0) memory state is retained that is Q and Qb retains their present values.…”

Section: Various Low Power Clocking Flip-flopsmentioning

confidence: 99%

“…The major disadvantages associated with CDMFF are that it is more prone to redundant switching events with the presence of a floating node in the circuit Figure 1(c) [8]. The CPSFF overcomes the problem of the floating node by grounding the M1 pMOS transistor thus charging the internal node through Vdd in Figure 1(c).…”

Section: Various Low Power Clocking Flip-flopsmentioning

confidence: 99%

“…CDFF works for both implicit as well as explicit pulse triggered flip-flop systems. In CDFF as shown in the Figure 1(a) [8], a special pulse generator circuit is used which generates clock pulse that help us to trigger the circuit at both positive and the negative edges as a result the whole system works on double edge triggered technology [9]. In CDFF the redundant switching activity is minimized by controlling the discharge path by using anMOS transistor at the bottom which is driven by input Qb.…”

Section: Introductionmentioning

confidence: 99%

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Designing a Novel Power Efficient D- Flip-Flop using Forced Stack Technique

Sharma¹,

Sethi²,

Dobriyal³

et al. 2013

IJCA

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In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30% to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce the power consumed by flip-flops and latches. In this paper various power efficient flip-flops with low power clock distribution network are examined. Among these flips-flops low Power Clocked Pass Transistor Flip-Flop (LCPTFF) consumes least power than Clocked Pair Shared Flip-Flop (CPSFF), Conditional Data Mapping Flip-Flop and Conditional Discharge Flip-Flop (CDFF). We propose a novel Low Power Forced Stack Clocked Pass Transistor Flip-Flop (LP-FSCPTFF) which reduces the power consumption by approximately 30.1% to 83.93% at 500MHz and 25.5% to 90.1% at 750MHz as compared to original LCPTFF. The simulation is carried out on Tanner EDA v13.0 at 90nm on different voltages at 500MHz and 750MHz. The temperature variation of different flip-flops is also shown at 5 °C, 2 5 °C and 50 °C.

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“…One of the foremost component inside the register is flip-flop. Flip-flop is the assembly of several gates, that function to reserve the logical states which is evoked by any data input signal as a response to clock pulses [1]. Flip-flop is employed to receive and store the data sequentially, during predetermi-ned clock interval.…”

Section: Introductionmentioning

confidence: 99%

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Purnomo¹,

Alhamidi²,

Wibisono³

et al. 2015

Jurnal Ilmu Komputer dan Informasi

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Register is one of the computer components that have a key role in computer organisation. Every computer contains millions of registers that are manifested by flip-flop. This research focuses on the investigation of flip-flop performance based on its type (D, T, S-R, and J-K) and architecture (structural, behavioural, and hybrid). Each type of flip-flop on each architecture would be tested in different bit of shift register with parallel load applications. The experiment criteria that will be assessed are power consumption, resources required, memory required, latency, and efficiency. Based on the experiment, it could be shown that D flip-flop and hybrid architecture showed the best performance in required memory, latency, power consumption, and efficiency. In addition, the experiment results showed that the greater the register number, the less efficient the system would be.

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A high performance D-flip flop design with low power clocking system using MTCMOS technique

Cited by 9 publications

References 6 publications

Leakage Reduction Technique and Analysis of CMOS D Flip Flop

Leakage Reduction Technique and Analysis of CMOS D Flip Flop

Designing a Novel Power Efficient D- Flip-Flop using Forced Stack Technique

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