A high-performance CMOS 70-MHz palette/DAC

Letham, L.; Ahuja, B.K.; Quader, K.; Mayer, Robert; Larsen, Roy; Canepa, G.

doi:10.1109/jssc.1987.1052853

Cited by 17 publications

(3 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…After the cell select decode, the select signal is latched and an inverter creates complimentary levels for the current switch formed by MS1 and MS2. The current source devices M1 and M2 create a cascoded current source, for high output resistance, and a high swing bias is used (10). Segment current sources use M current source transistor pairs to create the segment current.…”

Section: Dac Architecturementioning

confidence: 99%

A module generator for high-speed CMOS current output digital/analog converters

Neff

Gray

Sangiovanni-Vincentelli

1996

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

This paper presents a module generator for Digital/Analog Converter (DAC) circuits. A combination of circuit simulation and DAC design equations is used to estimate performance. A new constrained optimization method is used to determine design variable values. The layout is created using stretching and tiling operations on a set of primitive cells. Close coupling of optimization and layout allows accurate incorporation of layout parasitics in optimization. Prototypes have been demonstrated for an 8-bit, 100-MHz specification, driving a 37.5-ohm video load, and a static 10-bit specification, driving a 4mA full-scale output current. Both designs use a 5-V supply in a standard 1.2 µm CMOS process. 1

show abstract

Section: Dac Architecturementioning

confidence: 99%

A module generator for high-speed CMOS current output digital/analog converters

Neff

Gray

Sangiovanni-Vincentelli

1996

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…Among several CMOS DAC's proposed so far [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25], Some have a low conversion rate [10][11][12], while another has a large power consumption [12]. This paper describes a 12-bit 150 MHz CMOS current steering DAC.…”

Section: Introductionmentioning

confidence: 99%

A 12-b, 150 MHz Sample/s CMOS Current Steering D/A Converter with Gradient Error Compensation

Jiang

Wang²,

Wang

2006

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This paper discusses a circuit of 12-b, 150 MHz Sample/s current steering DAC with hierarchical symmetrical switching sequences which will compensate gradient error. The circuit of 12-b DAC employs segmented architecture, the least significant bits (LSB's) steer a binary weighted array, while the most significant bits (MSB's) are thermometer decoded and steer a unary array.The measured differential nonlinearity and integral nonlinearity are ±0.6 least significant bit (LSB) and ±0.9 LSB, respectively. The output spectrum of the DAC is −63 dB with an input frequency of 30 MHz at 150 MHz conversion rate. The circuit is fabricated in 0.5 μm, two-poly two-metal, 5.0 V, mixed-signal CMOS process and occupies 1.27 × 0.96 mm, when operating at 150 MHz Sample/s, it dissipates 91.6 mW from 5.0 V power supply which is much lower than those of [1].

show abstract

“…The mapped colors are decoded upon display using color palette by video palette DACs [1]. [2]. As the image resolution and color resolution increases, even 24-bit color displays will be ill-equipped to display truly high quality images, such as those from the 48-bit Kodak photo CD system, which still has to be color quantized to be displayed on 24-bit color displays.…”

Section: Introductionmentioning

confidence: 99%

A real-time scalable color quantizer trainer/encoder

Chaddha

Tan

Meng

Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers

View full text Add to dashboard Cite

In many color-imaging applications, it is desirable to display an image with as few different colors as possible with minimal loss in image quality. While good image quality is achievable using traditional Vector Quantization techniques. they are too slow for real-time vidm applications. An architectural design of a real-time, scalable color quantizer architecture is presented. It implements our fast Tree Structure Vector Quantization algorithm with a variable-size cubical prequantizer based on human perception proposed earlier. The design is scalable and uses different configurations of the processing and memory elements to process any 24-bit to 72-bit colors per input pixel to produce a 8-bit to 24-bit color palette.

show abstract

A high-performance CMOS 70-MHz palette/DAC

Cited by 17 publications

References 5 publications

A module generator for high-speed CMOS current output digital/analog converters

A module generator for high-speed CMOS current output digital/analog converters

A 12-b, 150 MHz Sample/s CMOS Current Steering D/A Converter with Gradient Error Compensation

A real-time scalable color quantizer trainer/encoder

Contact Info

Product

Resources

About