A 12-b, 150 MHz Sample/s CMOS Current Steering D/A Converter with Gradient Error Compensation

Abstract

This paper discusses a circuit of 12-b, 150 MHz Sample/s current steering DAC with hierarchical symmetrical switching sequences which will compensate gradient error. The circuit of 12-b DAC employs segmented architecture, the least significant bits (LSB's) steer a binary weighted array, while the most significant bits (MSB's) are thermometer decoded and steer a unary array.The measured differential nonlinearity and integral nonlinearity are ±0.6 least significant bit (LSB) and ±0.9 LSB, respectively. The output spectrum of the DAC is −63 dB with an input frequency of 30 MHz at 150 MHz conversion rate. The circuit is fabricated in 0.5 μm, two-poly two-metal, 5.0 V, mixed-signal CMOS process and occupies 1.27 × 0.96 mm, when operating at 150 MHz Sample/s, it dissipates 91.6 mW from 5.0 V power supply which is much lower than those of [1].

An I/Q channel 12-bit 120 MS/s CMOS DAC with deglitch circuits

“…Table 1. Most of conventional thermometer decoders suffer high current consumption and the error of delay time caused by the complexity of digital logic, resulting in decreasing the performance of DAC [7][8][9]. However, the 2 bit row and 2 bit column decoders employing the matrix switching decoder shown in Fig.…”

“…DAC architectures presented in [5][6][7][8][9] may be implemented in order to satisfy the requirements for a WLAN system. Based on these architectures, N-stage cascade of a thermometer decoder based M-bit sub-DAC, as illustrated in Fig.…”