A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for  nand-Type Flash Memory

Hsu, Tzu-Hsuan; Lue, Hang-Ting; King, Ya‐Chin; Hsieh, Jung-Yu; Lai, Erh-Kun; Hsieh, Kuang-Yeu; Liu, Rich; Lu, Chih‐Yuan

doi:10.1109/led.2007.895421

Cited by 35 publications

(31 citation statements)

References 11 publications

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“…As reported in Refs. [26][27][28][29][30][31], new NVM cell structures such as Hemi-Cylindrical FET (HCFET) and FinFET are proposed to address critical shortcomings of conventional MOSFET structure due to technology scaling.…”

Section: Technical Mitigation Approachesmentioning

confidence: 99%

The Impact of Tunnel Oxide Nitridation to Reliability Performance of Charge Storage Non-Volatile Memory Devices

Lee¹,

Wong²

2014

j. nanosci. nanotech.

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This paper is written to review the development of critical research on the overall impact of tunnel oxide nitridation (TON) with the aim to mitigate reliability issues due to incessant technology scaling of charge storage NVM devices. For more than 30 years, charge storage non-volatile memory (NVM) has been critical in the evolution of intelligent electronic devices and continuous development of integrated technologies. Technology scaling is the primary strategy implemented throughout the semiconductor industry to increase NVM density and drive down average cost per bit. In this paper, critical reliability challenges and key innovative technical mitigation methods are reviewed. TON is one of the major candidates to replace conventional oxide layer for its superior quality and reliability performance. Major advantages and caveats of key TON process techniques are discussed. The impact of TON on quality and reliability performance of charge storage NVM devices is carefully reviewed with emphasis on major advantages and drawbacks of top and bottom nitridation. Physical mechanisms attributed to charge retention and V(t) instability phenomenon are also reviewed in this paper.

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Section: Technical Mitigation Approachesmentioning

confidence: 99%

The Impact of Tunnel Oxide Nitridation to Reliability Performance of Charge Storage Non-Volatile Memory Devices

Lee¹,

Wong²

2014

j. nanosci. nanotech.

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“…CT cells have already been proposed as a suitable candidate to replace FGs below 40 nm but finally have not been used in 2D NAND [7][8][9][10][11][12].…”

Section: The Storage Method: Transitioning From Floating Gate To Charmentioning

confidence: 99%

“…For example, the use of a combination of a Hi-K metal gate and thicker oxide to improve both retention and erasing has been studied. Barrier Engineered (BE-SONOS) approach to CT [7][8][9][10][11][12] consists of replacing the trapping oxide with a stack of layers, O/N/O/N/O, so as to modify the band structure of the oxide in order to reduce the unwanted drawbacks of the structure ( Figure 5). …”

Section: The Storage Method: Transitioning From Floating Gate To Charmentioning

confidence: 99%

3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

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Abstract:In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a "punch-and-plug" process-with gate-all-around (GAA) cell devices-against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.

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“…9 In a bandgap engineered (BE)-SONOS device, the tunneling oxide of SONOS is replaced by a BE ONO layer. 10 Efficient hole tunneling occurs under the high E-field due to the band offset of the BE ONO layer, which allows fast erase speed. In these SONOS structures for high-speed program/erase, the charge trapping layer should be inserted in the gate dielectrics and thus it is hard to reduce the effective oxide thickness (EOT) of the gate dielectric for obtaining a high gate-to-channel coupling.…”

confidence: 99%

A SONOS device with a separated charge trapping layer for improvement of charge injection

Ahn

Moon

et al. 2017

AIP Advances

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A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

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A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand-Type Flash Memory

Cited by 35 publications

References 11 publications

The Impact of Tunnel Oxide Nitridation to Reliability Performance of Charge Storage Non-Volatile Memory Devices

The Impact of Tunnel Oxide Nitridation to Reliability Performance of Charge Storage Non-Volatile Memory Devices

3D NAND Flash Based on Planar Cells

A SONOS device with a separated charge trapping layer for improvement of charge injection

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