A high performance 90nm SOI technology with 0.992 μm/sup 2/ 6T-SRAM cell

Khare, Mukesh; Ku, S.H.; Donaton, R. A; Greco, S.; Brodsky, Colin J.; Chen, X.; Chou, A.; DellaGuardia, Ronald; Deshpande, Sadanand V.; Doris, B.; Fung, S.K.H.; Gabor, Allen H.; Gribelyuk, M.; Holmes, Steven J.; Jamin, F.; Lai, W.; Lee, W.H.; Li, Y.; McFarland, P.A.; Mo, R.; Mittl, S.; Narasimha, S.; Nielsen, Dennis; Purtell, R. J.; Rausch, W.; Sankaran, S.; Snare, J.; Tsou, L. Y.; Vayshenker, A.; Wagner, T.; Wehella-Gamage, D.; Wu, Ernest Y.; Wu, S.; Yan, Wendy; Barth, E.; Ferguson, Richard A.; Gilbert, P.; Schepis, D.; Sekiguchi, A.; Goldblatt, R.; Welser, J.J.; Müller, K.P.; Agnello, P.

doi:10.1109/iedm.2002.1175865

Cited by 34 publications

(8 citation statements)

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“…Table 1 shows the base parameters used in this study (note that Vdd and Id values are taken from [15], [16]). Values of interconnect pitch of metal layers in various 130nm and 90nm technologies are given in Table 2 [15], [16], [17], [18], [19], [20]. The global interconnect pitch of ITRS is twice the minimum value from ITRS [6].…”

Section: Via Blockagementioning

confidence: 99%

Investigation of performance metrics for interconnect stack architectures

Gupta

Kahng

Kim

et al. 2004

Proceedings of the 2004 International Workshop on System Level Interconnect Prediction

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This paper discusses metrics involving the bandwidth and energy characteristics of arbitrary interconnect stacks. Front-end dimensions are set by lithography and related fabrication restrictions and its performance is easily quantified using wellknown metrics such as FO4 or ring oscillator delays, Ioff, and Ion. Back-end dimensions are not similarly constrained yet there are no comparable back-end metrics. In this study we seek figures-ofmerit for interconnect architectures (stacks) that describe performance in terms of bandwidth and energy while considering issues such as via blockage and repeaters. A definition of bandwidth is presented and then appropriate via blockage models for interconnect stacks are investigated. In this paper, we improve existing bandwidth and throughput-driven design methodologies by looking at the entire stack rather than a single wiring layer. We also propose the use of bandwidth per unit energy. We evaluate and discuss these metrics in current 130nm and 90nm interconnect technologies.

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Section: Via Blockagementioning

confidence: 99%

Investigation of performance metrics for interconnect stack architectures

Gupta

Kahng

Kim

et al. 2004

Proceedings of the 2004 International Workshop on System Level Interconnect Prediction

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“…The 8T bit-cell adds 38 % area overhead relatively to the 6T cell. In more scaled CMOS technology such as 65 nm, 45 nm and beyond, the thin cell layout approach [12] might be effective to reduce the lithographic mismatch. But the area overhead may be remained in a same degree since both 6T and 8T cells will be scaled in asame way.…”

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confidence: 99%

An Advanced Embedded SRAM Cell with Expanded Read/Write Stability and Leakage Reduction

Chung¹

2012

Journal of IKEEE

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Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.Key words: SRAM, embedded memory, 8T cell, data stability, leakage current I . I n t r o duc tio n Technology scaling and increasing random variation in MOSFET characteristics reduce the operational margin of SRAM functionality. Most of current SRAM designs employ the 6-transistor (6T) memory bit-cell composed of two cross-coupled inverters with a set of access transistors. In this traditional 6T SRAM cell, the transistor strength ratios must be chosen such that the read static noise margin (SNM) and the write margin (WM) are both maintained, which presents conflicting constraints on the cell transistor strengths. This delicate balance of transistor strength ratios can be severely impacted by device variation, which dramatically degrades the cell operating margin in scaled technologies. Low supply voltages further exacerbate the problem since the threshold voltage variation consumes a large fraction of these voltage margins.To overcome this stability issue, many different structures of SRAM bit-cell have been explored. For examples, the 7T cell [1] may improve the read stability by cutting off a pull down path during read operation. But it has a limited write capability due to the single-ended write operation. The 8T [2-4], 9T [5] or 10T [6,7] SRAM cells decouple the data storage elements and the data output elements, and hence making the read SNM equal to the hold mode SNM. Write-ability is equal to that of the 6T cell. However, they do not have efficient column-interleaving structure in the write operation, which might be critical to cope with multi-bit errors. They also might suffer an access time degradation due to the single-ended read-bitline

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“…The circuit has been fabricated in a 90nm partially depleted digital CMOS SOI technology [6]. The test chip also contains a shift register to provide digital settings, and two inverter-based output buffers.…”

Section: Measurement Resultsmentioning

confidence: 99%

A 22 Gbit/s PAM-4 Receiver in 90nm CMOS-SOI Technology

Toifl

Menolfi

Ruegg³

et al.

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

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A receiver for PAM-4 encoded data signals is presented, which was measured to receive data at 22 Gbit/s with a BER<10 -12 at a maximum frequency deviation of 350 ppm and a 2 7 -1 PRBS pattern. We propose a novel voltage shifting amplifier to introduce a programmable offset to the differential data signal. A CML biasing scheme using programmable matched resistors limits the effect of process variations. The receiver also features a programmable signal termination, an analog equalizer and offset compensation for each sampling latch. Measured current consumption is 207 mA from a 1.1 V supply, active chip area is 0.12 mm 2 .

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A high performance 90nm SOI technology with 0.992 μm/sup 2/ 6T-SRAM cell

Cited by 34 publications

References 1 publication

Investigation of performance metrics for interconnect stack architectures

Investigation of performance metrics for interconnect stack architectures

An Advanced Embedded SRAM Cell with Expanded Read/Write Stability and Leakage Reduction

A 22 Gbit/s PAM-4 Receiver in 90nm CMOS-SOI Technology

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