An Advanced Embedded SRAM Cell with Expanded Read/Write Stability and Leakage Reduction

Abstract

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.Key words: SRAM, embedded memory, 8T cell, data stability, leakage current I . I n t r o duc tio n Technology scaling and increasing random variation in MOSFET characteristics reduce the operational margin of SRAM functionality. Most of current SRAM designs employ the 6-transistor (6T) memory bit-cell composed of two cross-coupled inverters with a set of access transistors. In this traditional 6T SRAM cell, the transistor strength ratios must be chosen such that the read static noise margin (SNM) and the write margin (WM) are both maintained, which presents conflicting constraints on the cell transistor strengths. This delicate balance of transistor strength ratios can be severely impacted by device variation, which dramatically degrades the cell operating margin in scaled technologies. Low supply voltages further exacerbate the problem since the threshold voltage variation consumes a large fraction of these voltage margins.To overcome this stability issue, many different structures of SRAM bit-cell have been explored. For examples, the 7T cell [1] may improve the read stability by cutting off a pull down path during read operation. But it has a limited write capability due to the single-ended write operation. The 8T [2-4], 9T [5] or 10T [6,7] SRAM cells decouple the data storage elements and the data output elements, and hence making the read SNM equal to the hold mode SNM. Write-ability is equal to that of the 6T cell. However, they do not have efficient column-interleaving structure in the write operation, which might be critical to cope with multi-bit errors. They also might suffer an access time degradation due to the single-ended read-bitline